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About the Reference Development Kit category
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0
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1720
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2 November 2014
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The Myriad RF and DEO – Nano development project kit installation procedure
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49
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6418
|
15 April 2021
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PLL Clock Input - Stand alone mode
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2
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1444
|
30 January 2020
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Myriad RF1 TX Test with external PLLCLK
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7
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1524
|
30 January 2020
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LMS6002D PLL is not loking
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0
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633
|
19 August 2019
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EVB7 board where to buy?
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3
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1230
|
2 July 2019
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What is LimeSDR-Mini_factory?
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1
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846
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5 March 2019
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Lime PCIE gateway project don't meet time requirements
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1
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696
|
14 February 2019
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SPI Problems, Pyboard
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41
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5841
|
29 January 2019
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TX/RX LPF DC offset Calibration on LMS6002D
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8
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4220
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22 December 2018
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uMyriadRF-LMS7002
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7
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3020
|
29 October 2018
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MyriadRF-1 Board with external on-board clock generator
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3
|
1603
|
23 October 2017
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Reference Dev Kit matching network and tuning
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4
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1272
|
3 October 2017
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LMS6002 RF loopback and AUXPA settings
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1
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1287
|
26 September 2017
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TDD mode
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7
|
2002
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29 August 2017
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Digital interface components
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8
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3591
|
15 May 2017
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Register test Vtune failed
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0
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1255
|
18 April 2017
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LMS6002D MyriadRF Dev Kit Application Note
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0
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1118
|
22 March 2017
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TX data format
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1
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1647
|
13 March 2017
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Myriad-RF 1 and Zipper - programming SI5351
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0
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1182
|
2 March 2017
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LMS6002d TX LO Leakage cancellation
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0
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1468
|
24 February 2017
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LMS6002D ADC setting problem
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0
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1135
|
8 February 2017
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MyriadRF SPI register readout issue
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3
|
1770
|
6 February 2017
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Read/Write to Myriad RF via SPI
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1
|
1600
|
28 January 2017
|
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Rx Functionality Myriad RF-1 + Zipper
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1
|
1483
|
28 January 2017
|
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30,72 clock
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7
|
3062
|
28 January 2017
|
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Zipper + Myriad RF Registers Test Failed
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1
|
1514
|
15 November 2016
|
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I would like to know the SPI command initialization sequence (Code)
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0
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1258
|
18 October 2016
|
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Myriad-RF Transmit I/Q Balance Calibration
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|
2
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2190
|
13 October 2016
|
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TX PLL programming (VCO and VCOCAP Code Selection)
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0
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1624
|
1 September 2016
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