What is the advantage of using TDD mode vs. FDD with both PLLs tuned to the same frequency and simply transmitting 0’s when receiving?
Hi, I am also interested in TDD mode. My question would be:
How long does a PLL take to lock up? I.e. how quickly can we switch between Tx and Rx?
If you see the related Google Group thread:
Also note that the LMS6002D documentation repository on GitHub has been updated to include a PDF with details of PLL settling time measurements:
Thanks Andrew, it was very helpful.
Which pll power off when turn to tdd mode? tx vco or rx vco?
or when tdd tx mode tx vco is work
whe tdd rx mode rx vco is work?
another question, tdd mode always only one antenna, switched to tx or rx by a gpio controlled. how to support one antenna in LMS6002 ? shall we place a chip on pcb to switch antenna?
thank a lot.
Hi lichen 813,
In TDD mode, Rx VCO is powered down during transmission and Tx VCO is power down during reception.
LMS6002D is a SISO design, which has TxRFOut pin and separate for RxRFIN pin. So, yes you will need to use RF switch to support one antenna.
Thanks andrew, I think this should be added into datasheet or programming docs.
Is there a GPIO available for switching an RF switch for TDD mode?