Now I am going to attach the zipper + 6002D to my FPGA development board (Arrow SoCKit) by HSMC. I power the zipper board by HSMC 12V by opening the SW1. But when I run registers test, TxPLL VTUNE and RxPLL VTUNE register failed. I use Windows 7 and the 6002D control software version is 2.4.1686.8239. Can anyone help me to solve this problem? Thank you so much.
addr: 0x04
Testing TxRF SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing TxRF SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x07
Testing RxFE SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing RxFE SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x06
Testing RxVga2 SPI, Mask 0xAA:
Module test with this pattern is OK.
addr: 0x05
Testing RxVga2 SPI, Mask 0x55:
Module test with this pattern is OK.
Testing RxLPF SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing RxLPF SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x03
Testing TxLPF SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing TxLPF SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x01
Testing TxPLL SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing TxPLL SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x02
Testing RxPLL SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing RxPLL SPI, Mask 0x55:
Module test with this pattern is OK.
addr: 0x00
Testing Top SPI, Mask 0xAA:
Module test with this pattern is OK.
Testing Top SPI, Mask 0x55:
Module test with this pattern is OK.
Testing TxPLL VTUNE registers:
Some problems with VTUNE registers:
VTUNE_H (should be/acctual): 1/1;
VTUNE_H (should be/acctual): 0/1;
VTUNE_L (should be/acctual): 1/1;
VTUNE_L (should be/acctual): 0/1;
Testing RxPLL VTUNE registers:
Some problems with VTUNE registers:
VTUNE_H (should be/acctual): 1/1;
VTUNE_H (should be/acctual): 0/1;
VTUNE_L (should be/acctual): 1/1;
VTUNE_L (should be/acctual): 0/1;