Lime PCIE gateway project don't meet time requirements


I am synthesizing the gateway project to LimePCIe in Quartus II 15.1, but the time requirements are not meet. Does anyone have the same problem?
How could I proceed in this situation?

I have never seen a Quartus project that passes the timing requirements, tho my exposure may not be that great. Anyhow, i would not worry about it.