I am having trouble with Tx/RX LPF DC offset calibration routine. I am following Flow chart 4.3 in Programming and calibration guide 1.4 Last modified 11/06/2013 13:29:00.
I am using zed board + zipper + Myriad RF board.
I power up the Zed board which in turn supplies power to the zipper and myriad rf board.
I than start LPF tuning module calibration:
(Flow chart 4.2)
I’ve tried to configure the lime chip for frequency, LPF BW and gains, and I’m still having the same problem.
Below is the steps that I followed to configure the chip:
write 07 02 – LPF to have 7 MHz cut off
write 10 5b – NINT and Nfrac for TX PLL
write 11 00
write 15 F9 – FREQSEL for tx PLL
write 34 0A – enable TX LPF and set cut off to 7MHz
write 45 88 – TXVGA2 configured to have a gain of 17 db
write 54 0A – enable RX LPF and set cut off to 7MHz
write 20 5b – NINT and NFRAC for RX PLL
write 21 00
write 25 F9 – FREQSEL for rx PLL
write 05 3e – Enable soft transmit and receive
write 09 45 – enable RX and TX DSM SPI clock
write 19 AF – configure VCOCAP, charge pump up offset current for Vtune
write 29 AF
write 17 e3
write 27 e3
read 1a 03 – Vtune in accpetable range
read 2a 03
write 47 40 – follow recommended setting in FAQ to increase performance
write 79 37
write 47
write 79
write 5f 9f – Power down DC offset comparator. Should be powered up only when DC offset cancellation algorithm is running
I have the same problem. What is the test mode?
I’ve tried the same step but it doesn’t work.
There are several registers related to the test mode in the register map but I don’t know how to control it.
If you look at Bit 0 of Register 0x54 for example there is a option to use DECODE control signals (which is normal use case) or to use Control signals from test mode registers.
If you look in the TABLE 11: RX LPF Configuration memory map (USER MODE) In the brackets it says user mode which i assume is the normal “Decode control signals”. If you flip to TABLE 14 there are some “TEST MODE” registers which is 5F by my guess.
So the registers in 5F for example do not take in effect unless the Control signals of bit 0 of 54 is switched to use test mode.
I’ve tried to configure the test mode(addr: 0x34 and 0x54), but it doesn’t work.
Calibration of TX LPF DC offset always results in 0x1F.
Can you share the register setting of TX LPF DC offset calibration?
I’ve tried several combinations of register setting, but it looks failure.