TX/RX LPF DC offset Calibration on LMS6002D


I am having trouble with Tx/RX LPF DC offset calibration routine. I am following Flow chart 4.3 in Programming and calibration guide 1.4 Last modified 11/06/2013 13:29:00.

I am using zed board + zipper + Myriad RF board.

I power up the Zed board which in turn supplies power to the zipper and myriad rf board.

I than start LPF tuning module calibration:
(Flow chart 4.2)

write 0x09 0x60 – enable lp cal clock
write 0x03 0x08
write 0x02 0x1f
write 0x03 0x18 – load in DC_CNTVAL
write 0x03 0x08
write 0x03 0x28 – START dc calibration
write 0x03 0x08
read 00 returns 0x1b

write 35 0x1b
write 55 0x1b

write 09 0x40 – Disaple lpf cal clock

This LPF tuning module seems to work now I move onto 4.3 and calibrate TX LPF:

write 0x09 0x42 – enable tx LPF cal clock
write 0x33 0x08
write 0x32 0x1f
write 0x33 0x18 – load in DC_CNTVAL
write 0x33 0x08
write 0x33 0x28 – START dc calibration
write 0x33 0x08
rs 30 returns 0x1f – This is equal to 31 therefore set 32 to zero and retry

write 0x32 0x00
write 0x33 0x18 – load in DC_CNTVAL
write 0x33 0x08
write 0x33 0x28 – START dc calibration
write 0x33 0x08
rs 30 returns 0x00 – FAILURE PANIC: Algorithm does not Converge!

Now I am panicing…

Am I doing something wrong? Am I supposed to configure PLL and other registers before doing this calibration?

Any insight would be helpful.



The calibration has to be executed when the chip is configured for frequency, LPF BW and gains. Try to do this first and the execute calibrations.


Thanks Rich,

I’ve tried to configure the lime chip for frequency, LPF BW and gains, and I’m still having the same problem.

Below is the steps that I followed to configure the chip:

write 07 02 – LPF to have 7 MHz cut off
write 10 5b – NINT and Nfrac for TX PLL
write 11 00
write 15 F9 – FREQSEL for tx PLL
write 34 0A – enable TX LPF and set cut off to 7MHz
write 45 88 – TXVGA2 configured to have a gain of 17 db
write 54 0A – enable RX LPF and set cut off to 7MHz
write 20 5b – NINT and NFRAC for RX PLL
write 21 00
write 25 F9 – FREQSEL for rx PLL
write 05 3e – Enable soft transmit and receive

write 09 45 – enable RX and TX DSM SPI clock
write 19 AF – configure VCOCAP, charge pump up offset current for Vtune
write 29 AF
write 17 e3
write 27 e3
read 1a 03 – Vtune in accpetable range
read 2a 03

write 47 40 – follow recommended setting in FAQ to increase performance
write 79 37
write 47
write 79

write 5f 9f – Power down DC offset comparator. Should be powered up only when DC offset cancellation algorithm is running

write 09 65 – DC offset calibration clock enabled, flow chart 4.2
write 03 08 – LPF tuning module selected
write 03 28 – star calibration
write 03 08 – deactive start calibration command
read 00 1d
write 35 1d – write DCCAL value to TX and RXLPF resistor calibration control
write 55 1d
write 09 45 – restore clock enable

write 09 47 – TX LPF DC offset calibration clock enabled, flow chart 4.3
write 33 08 – select I filter for calibration module
write 33 28 – start calibration
write 33 08 – deactive start calibration
read 30 1f
write 32 00 – write 0 to DC_CNTVAL to be loaded
write 33 18 – load value from DC_CNTVAL to module
write 33 08 – deactivate load value command
write 33 28 – start calibration
write 33 08 – deactive start calibration
read 30 1f

I’m unsure if 1f is a valid response.

With such configuration. we have no problem running BB and RF loopback. We’ve tried another myraid board and got similar results.


I think the issue is with register 0x5F setting. Set PD_DCOCMP_LP register to ‘1F’ before calibration and to ‘9F’ after calibration is finished.

Also try to power down dac before calibration, register 0x57, [7] EN_ADC_DAC - ‘0’.


Yes we figured it out via email with you.

The problem was indeed with 0x5F but we could not get it to take effect until we enabled test mode in register 54.

We noticed that it was disabled by default when Test mode is off. When you Enable test mode it will enable the DC offset comparators by default.

So basically we turn on the Test mode and calibrate than turn off test mode. We don’t have to touch 5F or 3F. Does this make sense??

Also we are the engineers from Canada who have been emailing you about TX Unwanted Side band issues yesterday.

Thanks for replying



I have the same problem. What is the test mode?
I’ve tried the same step but it doesn’t work.
There are several registers related to the test mode in the register map but I don’t know how to control it.



If you look at Bit 0 of Register 0x54 for example there is a option to use DECODE control signals (which is normal use case) or to use Control signals from test mode registers.

If you look in the TABLE 11: RX LPF Configuration memory map (USER MODE) In the brackets it says user mode which i assume is the normal “Decode control signals”. If you flip to TABLE 14 there are some “TEST MODE” registers which is 5F by my guess.

So the registers in 5F for example do not take in effect unless the Control signals of bit 0 of 54 is switched to use test mode.

Thanks Cory,

I’ve tried to configure the test mode(addr: 0x34 and 0x54), but it doesn’t work.
Calibration of TX LPF DC offset always results in 0x1F.
Can you share the register setting of TX LPF DC offset calibration?
I’ve tried several combinations of register setting, but it looks failure.


Is this problem solved?