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limeNET micro + limeSDR with rockPI 4 + AI CORE XM
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1
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July 31, 2019
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LMS8001A Question
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3
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July 18, 2019
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Multiple LMS chips SPI issue
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10
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July 16, 2019
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Lime working with non-pc. What mobo? What OS?
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9
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July 13, 2019
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Running MCU Calibration via LimeSuite
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8
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July 5, 2019
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Producer Support
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2
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June 13, 2019
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IA, IB phase mismatch
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7
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June 11, 2019
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Transmitter Output Level
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9
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June 11, 2019
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Lime Microcontroller Calibration
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8
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June 5, 2019
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Noise in Rx I and Q
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9
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May 27, 2019
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Single Tone Tx
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11
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May 22, 2019
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MIMO DDR mode LML interface
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4
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May 21, 2019
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Clocking architecture for multiple LMS chips
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1
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May 20, 2019
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TxTSG output
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17
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May 16, 2019
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LMS7002 Assembly Guidelines
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3
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May 14, 2019
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Writing a register of LMS7002M
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2
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May 7, 2019
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What is frame, sample source in position x and limelight interface settings?
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2
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May 2, 2019
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How to calibrate IQ imbalance correction in LMS7002m
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2
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May 2, 2019
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LMS6002 - big problem with PLL lock time for FDD and TDD modes
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3
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April 5, 2019
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LMS6002 - What is "ADC sampling phase" parameter means?
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3
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April 4, 2019
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Super frustrated
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14
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March 26, 2019
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DVB-T using limesdr in GNU-Radio with QPSK,16QAM and 64QAM
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2
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March 18, 2019
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Why are the waveforms disappeared in FFT viewer after caculation and tunning?
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5
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March 9, 2019
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What is the relationship between the channels and ports?
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1
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February 20, 2019
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Is the block diagram right or wrong?
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1
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February 18, 2019
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How to change the frequency of MCK1 and MCLK2 except CLKGEN settings
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2
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February 20, 2019
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There are not data on the limelight port
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5
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January 31, 2019
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How to configurate the sole voltage system with inner LDO?
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5
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January 29, 2019
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Could you pls help me to check the connection of unused volatage pins?
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3
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January 23, 2019
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Could you explain the timing diagramm for me?
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4
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January 21, 2019
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