|
IA, IB phase mismatch
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7
|
June 11, 2019
|
|
Transmitter Output Level
|
9
|
June 11, 2019
|
|
Lime Microcontroller Calibration
|
8
|
June 5, 2019
|
|
Noise in Rx I and Q
|
9
|
May 27, 2019
|
|
Single Tone Tx
|
11
|
May 22, 2019
|
|
MIMO DDR mode LML interface
|
4
|
May 21, 2019
|
|
Clocking architecture for multiple LMS chips
|
1
|
May 20, 2019
|
|
TxTSG output
|
17
|
May 16, 2019
|
|
LMS7002 Assembly Guidelines
|
3
|
May 14, 2019
|
|
Writing a register of LMS7002M
|
2
|
May 7, 2019
|
|
What is frame, sample source in position x and limelight interface settings?
|
2
|
May 2, 2019
|
|
How to calibrate IQ imbalance correction in LMS7002m
|
2
|
May 2, 2019
|
|
LMS6002 - big problem with PLL lock time for FDD and TDD modes
|
3
|
April 5, 2019
|
|
LMS6002 - What is "ADC sampling phase" parameter means?
|
3
|
April 4, 2019
|
|
Super frustrated
|
14
|
March 26, 2019
|
|
DVB-T using limesdr in GNU-Radio with QPSK,16QAM and 64QAM
|
2
|
March 18, 2019
|
|
Why are the waveforms disappeared in FFT viewer after caculation and tunning?
|
5
|
March 9, 2019
|
|
LMS7002M RF Matching
|
3
|
February 27, 2019
|
|
What is the relationship between the channels and ports?
|
1
|
February 20, 2019
|
|
Is the block diagram right or wrong?
|
1
|
February 18, 2019
|
|
How to change the frequency of MCK1 and MCLK2 except CLKGEN settings
|
2
|
February 20, 2019
|
|
There are not data on the limelight port
|
5
|
January 31, 2019
|
|
How to configurate the sole voltage system with inner LDO?
|
5
|
January 29, 2019
|
|
Could you pls help me to check the connection of unused volatage pins?
|
3
|
January 23, 2019
|
|
Could you explain the timing diagramm for me?
|
4
|
January 21, 2019
|
|
How to database signal reception?
|
4
|
January 20, 2019
|
|
40MHz replay garage opener trouble
|
1
|
January 4, 2019
|
|
Changing the Channel Bandwidth on GNURadio
|
1
|
November 23, 2018
|
|
LMS7002M 180 degree phase jump
|
10
|
November 19, 2018
|
|
Using the reserved register is legal or not?
|
2
|
November 12, 2018
|
