I was really disappointed to find that the center frequency on the LimeSDR-USB won’t go below 30MHz. Setting a sample rate high enough to tune in even 25 MHz (as 5MHz lower sideband) puts an enormous strain on the computer being fed by the SDR to do digital band-pass filtering and decimation to pick out an audio-bandwidth slice of HF frequency.
So, is there any way to put that computational work onto the FPGA chip, so that the host computer only has to receive samples at a base-band sample rate (ex.: 48kHz) that are from a programmed slice of the lower sideband (i.e., -4.5MHz +/- 20kHz)? If so, how does one set it up? Even better, could the FPGA be programmed to do it for several different slices (same slice width) so multiple HF channels could be monitored with independent audio-speed sample streams (i.e., 4 different I/Q audio sample streams multiplexed together)?