How to do HF decimation on FPGA instead of host computer

System Development
#1

I was really disappointed to find that the center frequency on the LimeSDR-USB won’t go below 30MHz. Setting a sample rate high enough to tune in even 25 MHz (as 5MHz lower sideband) puts an enormous strain on the computer being fed by the SDR to do digital band-pass filtering and decimation to pick out an audio-bandwidth slice of HF frequency.

So, is there any way to put that computational work onto the FPGA chip, so that the host computer only has to receive samples at a base-band sample rate (ex.: 48kHz) that are from a programmed slice of the lower sideband (i.e., -4.5MHz +/- 20kHz)? If so, how does one set it up? Even better, could the FPGA be programmed to do it for several different slices (same slice width) so multiple HF channels could be monitored with independent audio-speed sample streams (i.e., 4 different I/Q audio sample streams multiplexed together)?

#2

Use the TSP. It will not drop the bandwidth down to 48kHz though, but you can decimate by 2,4,8,16 or 32

#3

Not quite what I need. The TSP documentation you referenced says that the decimation occurs before the filtering, which doesn’t give me what I need, which is band-pass filtering before decimation, so I can accurately extract just the slice of the lower sideband I need.

That’s why I was wondering if I could run a decimation program on the Cyclone chip to reduce the amount of data that would have to be processed on the general-purpose computer downstream (assuming the TSP does the band-pass filtering), and similarly upsampling in the other direction to create a HF SSB transceiver.

#4

Ah, now I see. I didn’t realize that the TSP mixer was a separate unit from the front end mixer with the restricted VCO range. Double conversion, how nice.

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#5

The TSP is all digital, it is after the ADC. Look where it sits in the block diagram.

#6

For HF TSP decimation is limited with NCO limits. I could not find way to set NCO more than 1/2 of the sample rate (Nyquist limit?). In the LMS7002 document it say only how equation look like and mention NCO drive Fclk but not how it can be changed? For entire HF minimum sample rate is 1.875MHz. Even 10 year old dual or quad core PC is fast enough for this task.
Qestion is still remain: is it posible to change NCO more than half of sample rate?

#7

My guess would be Nyquist limit, so maybe increase the sample rate ? It can go quite high. You will need to decimate it afterwards within the TSP to be less than the ~60MHz of bandwidth possible from the digital interface out from the TSP. Maybe even shift your centre frequency higher (or not) for a higher sample rate. The more you decimate the higher the dynamic range, but you will probably need to add an external lowpass/bandpass filter to limit unwanted signals (e.g. Look at the filters on the LimeRFE board).

I’ll point you to this thread where I learned about the NCO and decimation. Which is not that long ago actually.

#8

I did play with NCO before ( https://github.com/GoranRadivojevic/sdrsharp-limesdr ) but never study internal structure of LMS7002 chip (only LMS API calls). Now after seeing block diagram of decimator I wonder is the decimator stages built into silicone or can be reprogrammed? Description for decimator (part 11.11 Decimation) says that chip have 5 stages, each stage decimate by 2. If stages can be reprogrammed than we can have decimation more then 32 even if we sacrifice alias suppression but if the decimator is in silicone 32 is maximum.

#9

The lowest level document for the LMS7002M that I know about is the public information on the SPI Registers published in 2015: