We have built a custom board with the provision for connecting multiple LMS7002M daughter boards.
The SPI connected in a star topology with a processor acting as the SPI master.
When only one daughter board is connected the SPI interface works fine but when more than one are connected then the SPI doesn’t work correctly (for instance the version read command gives back an incorrect version number and this is different each time).
It looks like pin drivers of SPI master are not strong enough to drive multiple slaves.
Try to decrease SPI bus frequency.
We checked the SPI lines with a logic analyzer and found that the SCLK, MOSI and CS lines are fine, but there is jitter on the MISO lines when more than one boards are connected.
Yes, MISO line from LMS7 doesn’t go to Z state when inactive. Hence you get multiple outputs connected to one input. That’s the issue.
Ok, so what do we do?
MISO lines from LMS7 chip can be combined via external “OR” component and then fed to SPI master MISO line.
Another option would be to connect each MISO line from LMS7 to buffer component. Control buffer output enable signal from appropriate SEN line.
Unfortunately both the options are not feasible for us, the boards have been made.
That’s the only options I can think off right now.
One more possibility is to involve internal LMS7 MCU by implementing communication via I2C.
One more solution in your case would be 3 wire LMS7002M SPI interface instead of 4. In this case SPI MOSI line (LMS7002M pin SDIO) will be bidirectional. If LMS7002M is not selected by SEN, then SDIO line is as input and will not drive the line. If LMS7002M is selected by SEN, then it will be as input during SPI write operation and as output for last 16 SPI clock cycles during read operation. Hope this helps.
Thank you for the input, it looks interesting. Will try it.