The problem: the J7 SPI’s SDO (serial port data Output) is all-‘0’s (pulled low) when trying to read any register. The SDO pin goes High only when the SAEN pin (slave-enable, chip-select) goes inactive (high).
The attached scope capture is taken while reading the MAC register (at 0x0020), where it should have exhibit all-‘1’s (0xFFFF). The phenomenon is the same for other registers Read cycle as well.
The bottom scope channel shows the SPI clock (SCLK).
Not shown is the SDIO pin (serial port data Input), which has 0x0020 – where bit 15 is ‘0’ for ‘Read’, transmitted MSBit first, under “SPI Mode 0”.
The SPI rate is 2 MHz.
Settings:
- The LMS7002 board is stand-alone (No FPGA board is connected to the FMC connector J6).
- Resistors R91, R92, R93, R94, R95 and R96 are not mounted on the board (NF), as specified in Table 5 “SPI Control Options” of section 6.3.3 “SPI Control Configuration” of your “LMS7002M Quick Starter Manual for EVB7 kit” manual.
- SW1 “RST” is ON, shorting to GND, holding the ATMEL (USB<–>SPI converter) processor in HW Reset; thus its pins are in High-Z. This is not specified in your manual, but looking at the schematics it turns out to be a good idea to do so.
- The USB connector is left empty – no cable is connected (to PC).
- The LMS7002 board is connected to a Freescale FRDM-K64F evaluation board, acting as the SPI master. The wiring connection is as follows:
FRDM-K64F Lime Micro 7002
Header K64F Pin Function Header J7 LM Pin Name
J2 - 12 PTD1 SPI0 - SCK J7 - 41 SCLK (spi clk in)
J2 - 8 PTD2 SPI0 - SOUT J7 - 42 SDIO (data input)
J2 - 10 PTD3 SPI0 - SIN J7 - 43 SDO (data output)
J2 – 6 PTD0 SPI0 – PCS0 (CS) J7 - 40 SAEN (slave en)
J2 - 14 — GND J7 – 20 GND
J1 - 12 PTA2 GPIO for LM Reset J7 - 44 Reset
J1 - 4 PTC17 GPIO for LM TXEN J7 - 18 TXEN
J1 - 2 PTC16 GPIO for LM RXEN J7 – 38 RXEN