Custom LMS7002M board debugging

System Development
1

Hi,

I’ve recently completed a board design based on LMS7002M & Xilinx Zynq device.

I am now at the stage where the Zynq side of the design is operating properly & I have a control interface to the LMS7002M via SPI & the Myriad RF LMS7002M driver layer under petalinux. I do not have tested RTL code in place for the LimeLight interface yet, but I wanted to validate as much of the design as possible at this early stage, as I believe I should be able to run the device calibrations & confirm a lot of functionality without a fully functional BB interface.

I am basing my initial work on test/access_test.c, which is part of the https://github.com/myriadrf/LMS7002M-driver.

The reference clock in my design was modified to 32MHz in order to simplify certain aspects of the final application, but I do not believe this should have any bearing as long as the correct modifications have been made.

The initial stages of the device setup & VCO tuning etc appear to work successfully, however the LMS7002M_rbb_set_filter_bandwidth() & LMS7002M_tbb_set_filter_bandwidth() functions fail for both CHA & CHB.

Obviously as this is an untested board, I’m aware there’s an awful lot of things that could be wrong at this point. Really I’m after pointers on the best ways to spend my time understanding how to proceed.

The actual errors are:-

[ERROR] failed to converge when calibrating cfb_tia_rfe
[ERROR] failed to cal rcal_lpflad_tbb

And they appear to happen because cal_read_rssi() always returns 0.

Below is the complete debug output, (sorry if it’s a bit large!).

Best regards,
Paul Armitt

@ZynqRadioUSB:~# LMS7002Test /dev/spidev1.0

== Test LMS7002M access (v2)

Read sentinel 0x0
Create LMS7002M instance
rev 0x1
ver 0x7
[INFO] CGEN tune 64.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] Using: fdiv = 42, Ndiv = 84.000000, fvco = 2688.000000 MHz
[DEBUG] fdiv = 42, Ndiv = 84.000000, Nint = 84, Nfrac = 0, fvco = 2688.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 215, highest CSW_VCO 221
[DEBUG] lowest CSW_VCO 215, highest CSW_VCO 221, CSW_VCO 218
[DEBUG] VCO OK
======== Tune the frontends =========
[INFO] SXX tune 2500.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 312.500000, fvco = 10000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 625.000000, fvco = 20000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=1, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 220, highest CSW_VCO 225
[DEBUG] lowest CSW_VCO 220, highest CSW_VCO 225, CSW_VCO 222
[DEBUG] VCO OK
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
[DEBUG] Testing for SEL_VCO = 1
[DEBUG] VCO select FAIL - too high
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
0 - Actual TX LO freq 2500.000000 MHz
[INFO] SXX tune 2500.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, fvco = 5000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 312.500000, fvco = 10000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 625.000000, fvco = 20000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 219, highest CSW_VCO 223
[DEBUG] lowest CSW_VCO 219, highest CSW_VCO 223, CSW_VCO 221
[DEBUG] VCO OK
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
[DEBUG] Testing for SEL_VCO = 1
[DEBUG] VCO select FAIL - too high
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 2, Ndiv = 156.250000, Nint = 152, Nfrac = 262144, DIV_LOCH_SX = 0, fvco = 5000.000000 MHz
0 - Actual RX LO freq 2500.000000 MHz
======== Set and calibrate RX:A =========
[INFO] CGEN tune 200.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] Using: fdiv = 12, Ndiv = 75.000000, fvco = 2400.000000 MHz
[DEBUG] fdiv = 12, Ndiv = 75.000000, Nint = 75, Nfrac = 0, fvco = 2400.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 174
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 174, CSW_VCO 171
[DEBUG] VCO OK
[INFO] SXX tune 500.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 250.000000, fvco = 8000.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 500.000000, fvco = 16000.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 1000.000000, fvco = 32000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 250.000000, fvco = 8000.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 500.000000, fvco = 16000.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 1000.000000, fvco = 32000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, Nint = 121, Nfrac = 0, DIV_LOCH_SX = 2, fvco = 4000.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 49, highest CSW_VCO 55
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 49, highest CSW_VCO 55, CSW_VCO 52
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 125.000000, Nint = 121, Nfrac = 0, DIV_LOCH_SX = 2, fvco = 4000.000000 MHz
[INFO] SXX tune 499.950000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 16, Ndiv = 249.975000, fvco = 7999.200000 MHz
[DEBUG] fdiv = 32, Ndiv = 499.950000, fvco = 15998.400000 MHz
[DEBUG] fdiv = 64, Ndiv = 999.900000, fvco = 31996.800000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 16, Ndiv = 249.975000, fvco = 7999.200000 MHz
[DEBUG] fdiv = 32, Ndiv = 499.950000, fvco = 15998.400000 MHz
[DEBUG] fdiv = 64, Ndiv = 999.900000, fvco = 31996.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, Nint = 120, Nfrac = 1035468, DIV_LOCH_SX = 2, fvco = 3999.600000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=0
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 48, highest CSW_VCO 55
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 48, highest CSW_VCO 55, CSW_VCO 51
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 124.987500, Nint = 120, Nfrac = 1035468, DIV_LOCH_SX = 2, fvco = 3999.600000 MHz
[DEBUG] rssi_value_50k = 0
[INFO] SXX tune 490.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 245.000000, fvco = 7840.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 490.000000, fvco = 15680.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 980.000000, fvco = 31360.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 245.000000, fvco = 7840.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 490.000000, fvco = 15680.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 980.000000, fvco = 31360.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, Nint = 118, Nfrac = 524288, DIV_LOCH_SX = 2, fvco = 3920.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 31, highest CSW_VCO 37
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 31, highest CSW_VCO 37, CSW_VCO 34
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 122.500000, Nint = 118, Nfrac = 524288, DIV_LOCH_SX = 2, fvco = 3920.000000 MHz
[DEBUG] cal_read_rssi (iter 1) = 0
…
[DEBUG] cal_read_rssi (iter 512) = 0
[ERROR] failed to converge when calibrating cfb_tia_rfe
[ERROR] rx_cal_tia_rfe() failed
======== Set and calibrate TX:A =========
[INFO] CGEN tune 200.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] Using: fdiv = 12, Ndiv = 75.000000, fvco = 2400.000000 MHz
[DEBUG] fdiv = 12, Ndiv = 75.000000, Nint = 75, Nfrac = 0, fvco = 2400.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 174
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 174, CSW_VCO 171
[DEBUG] VCO OK
[ERROR] failed to cal rcal_lpflad_tbb -> -3
[ERROR] tx_cal_tbb_lpf() failed
======== Set and calibrate RX:B =========
[INFO] CGEN tune 200.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] Using: fdiv = 12, Ndiv = 75.000000, fvco = 2400.000000 MHz
[DEBUG] fdiv = 12, Ndiv = 75.000000, Nint = 75, Nfrac = 0, fvco = 2400.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 175
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 175, CSW_VCO 171
[DEBUG] VCO OK
[INFO] SXX tune 500.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 250.000000, fvco = 8000.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 500.000000, fvco = 16000.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 1000.000000, fvco = 32000.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.250000, fvco = 1000.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.500000, fvco = 2000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, fvco = 4000.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 250.000000, fvco = 8000.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 500.000000, fvco = 16000.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 1000.000000, fvco = 32000.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 125.000000, Nint = 121, Nfrac = 0, DIV_LOCH_SX = 2, fvco = 4000.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 55, highest CSW_VCO 58
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 55, highest CSW_VCO 58, CSW_VCO 56
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 125.000000, Nint = 121, Nfrac = 0, DIV_LOCH_SX = 2, fvco = 4000.000000 MHz
[INFO] SXX tune 499.950000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 16, Ndiv = 249.975000, fvco = 7999.200000 MHz
[DEBUG] fdiv = 32, Ndiv = 499.950000, fvco = 15998.400000 MHz
[DEBUG] fdiv = 64, Ndiv = 999.900000, fvco = 31996.800000 MHz
[DEBUG] fdiv = 2, Ndiv = 31.246875, fvco = 999.900000 MHz
[DEBUG] fdiv = 4, Ndiv = 62.493750, fvco = 1999.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, fvco = 3999.600000 MHz
[DEBUG] fdiv = 16, Ndiv = 249.975000, fvco = 7999.200000 MHz
[DEBUG] fdiv = 32, Ndiv = 499.950000, fvco = 15998.400000 MHz
[DEBUG] fdiv = 64, Ndiv = 999.900000, fvco = 31996.800000 MHz
[DEBUG] fdiv = 8, Ndiv = 124.987500, Nint = 120, Nfrac = 1035468, DIV_LOCH_SX = 2, fvco = 3999.600000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 53, highest CSW_VCO 57
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 53, highest CSW_VCO 57, CSW_VCO 55
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 124.987500, Nint = 120, Nfrac = 1035468, DIV_LOCH_SX = 2, fvco = 3999.600000 MHz
[DEBUG] rssi_value_50k = 0
[INFO] SXX tune 490.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 245.000000, fvco = 7840.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 490.000000, fvco = 15680.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 980.000000, fvco = 31360.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 30.625000, fvco = 980.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 61.250000, fvco = 1960.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, fvco = 3920.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 245.000000, fvco = 7840.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 490.000000, fvco = 15680.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 980.000000, fvco = 31360.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 122.500000, Nint = 118, Nfrac = 524288, DIV_LOCH_SX = 2, fvco = 3920.000000 MHz
[DEBUG] Testing for SEL_VCO = 0
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 35, highest CSW_VCO 39
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=1
[DEBUG] i=2, hi=1, lo=1
[DEBUG] i=1, hi=1, lo=1
[DEBUG] i=0, hi=1, lo=1
[DEBUG] lowest CSW_VCO 256, highest CSW_VCO 128
[DEBUG] lowest CSW_VCO 35, highest CSW_VCO 39, CSW_VCO 37
[DEBUG] VCO OK
[DEBUG] Choosing SEL_VCO = 0
[DEBUG] fdiv = 8, Ndiv = 122.500000, Nint = 118, Nfrac = 524288, DIV_LOCH_SX = 2, fvco = 3920.000000 MHz
[DEBUG] cal_read_rssi (iter 1) = 0
…
[DEBUG] cal_read_rssi (iter 512) = 0
[ERROR] failed to converge when calibrating cfb_tia_rfe
[ERROR] rx_cal_tia_rfe() failed
======== Set and calibrate TX:B =========
[INFO] CGEN tune 200.000000 MHz (fref=32.000000 MHz) begin
[DEBUG] Using: fdiv = 12, Ndiv = 75.000000, fvco = 2400.000000 MHz
[DEBUG] fdiv = 12, Ndiv = 75.000000, Nint = 75, Nfrac = 0, fvco = 2400.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=1, lo=1
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 175
[DEBUG] lowest CSW_VCO 168, highest CSW_VCO 175, CSW_VCO 171
[DEBUG] VCO OK
[ERROR] failed to converge when calibrating rcal_lpflad_tbb
[ERROR] tx_cal_tbb_lpf() failed
Debug setup!
Press ctrl+c to exit

1 Like
2

Hi @paularmitt,

As far as I understand, you are implementing calibration procedures in Zynq CPU, correct?

I would suggest to use LMS7002M MCU firmware provided for this task, as described here:
https://wiki.myriadrf.org/LMS7002Mr3_Calibration_Using_MCU

1 Like
3

Hi Zack,

Thanks for getting back - that is completely correct. I am currently using the LMS7002M-driver from yourselves running on the Zynq CPU, routing SPI via EMIO.

I had intended to transition over to MCU based calibration after I verified the driver functionality. My concern is that I have some underlying problem (i.e. board related) that is causing the driver-based calibration to fail. The MCU based calibration is very opaque, and I did not want to be in a situation where it fails & I have no understanding why.

If you believe there is some problem with my current approach, I will get the MCU method up and running & then get back to you with my results.

Best regards,
Paul

4

Hi @paularmitt,

It looks like you are communicating with LMS7002M correctly (you can read from the registers what you write). If yes, then there is no reason to avoid calibration using LMS7002M MCU.

5

Hi Zack,

Yes, the SPI interface is working fine as I have no trouble writing & reading back registers.

My understanding was that the driver layer I am using implements the same calibration routines as the MCU (or thereabouts) so the fact that the filter tuning fails troubles me. I am concerned for instance that parts of my device may not be powered correctly, or that I have made some other schematic error. I have replicated the LimeSDR / UNITE7002 scheme as closely as possible, but there’s always the chance something has eluded me.

I will get back to you (probably tomorrow now) with the results of my MCU testing.

Thanks again,
Paul

6

Hi @Zack,

Apologies for the delay in getting back - the MCU calibration mechanism seems to operate successfully. I may port the MCU calibration code over to my driver layer at some point to increase visibility - I hadn’t realised this was available in the LimeSuite source tree when we talked the other day.

During impementation of the spi upload I did come a minor issue with the instructions at https://wiki.myriadrf.org/LMS7002Mr3_Calibration_Using_MCU

For your reference, 2.2.1. Step 3 “Wait until MCU programming buffer is empty” incorrectly states that register 0x0003 bit 0 reports 0 when buffer is empty. This is incorrect, as a ‘1’ in this bit position signals the FIFO is empty. I’d also say that the sense of this bit (and some others) are not clear in the SPI register map document I have been using.

Anyway, that’s positive progress as I can now concentrate on getting my LimeLight layer up & running!

Thanks again,
Paul