Single tone generator test + sequence for other tests

General Discussion
1

Hello,
We have built a custom board and have a working SPI interface to it.

  1. To test the analog interface between the LMS output to the RF connector it will be useful to generate a single tone.
    Is there a mode in the LMS7002 that can generate a single tone? In the git repo we found some file doing that but wanted to know if it is the right one.
    If yes, may I ask if someone could point us to the sequence of setting this up.

  2. Is there a pattern generator inside the chip to verify the digital interface between the LMS ADC output and our FPGA.

  3. How is the external clock xoscin_rx configured? And how is the tx made to use the same.

  4. May I ask you to please advise on a step by step method of testing the different functions of the the LMS. There are many things that need to be configured (dc calibration, vco calibration, filter calibration etc…) what will be the right sequence to do that.
    Thank you for all your help in advance,

2

Will not answer all the questions at once, bear with me please. Assuming you have Programming and calibration guide.

(1) - Two options here: (a) you can generate single tone using TxTSG which is quite poor and can generate two frequencies only - clock of TxTSP divided by 4 or by 8 and divided by interpolation factor; (b) you can generate single tone using TxNCO. For option (a) you bypass all the modules in TxTSP except interpolation, set to provide data from TxTSG instead of LML interface (INSEL 0x0200[2] = 1) and control generated frequency by TSGFCW 0x0200[8:7].

(2) You can use the same approac as in (1) just other way round. You just provided RxTSG data instead of ADC. Check RxTSP control diagram in Programming and calibration guide.

(3) Check XBUF control diagram in Programming and calibration guide.

3

Hello Zack,
Thank you for your inputs.

Since then the development is as follows:

  1. LMS7002M_set_data_clock PASSES. Settings: REF_FREQ = 50e6, FOUT = 100e6

  2. Then the following are enabled:
    //enable components
    LMS7002M_afe_enable(lms, LMS_TX, LMS_CHA, true);
    LMS7002M_afe_enable(lms, LMS_TX, LMS_CHB, true);
    LMS7002M_afe_enable(lms, LMS_RX, LMS_CHA, true);
    LMS7002M_afe_enable(lms, LMS_RX, LMS_CHB, true);
    LMS7002M_rxtsp_enable(lms, LMS_CHAB, true);
    LMS7002M_txtsp_enable(lms, LMS_CHAB, true);
    LMS7002M_rbb_enable(lms, LMS_CHAB, true);
    LMS7002M_tbb_enable(lms, LMS_CHAB, true);
    LMS7002M_rfe_enable(lms, LMS_CHAB, true);
    LMS7002M_trf_enable(lms, LMS_CHAB, true);
    LMS7002M_sxx_enable(lms, LMS_RX, true);
    LMS7002M_sxx_enable(lms, LMS_TX, true);

  3. LMS7002M_set_lo_freq(lms, LMS_TX, REF_FREQ, 2.500e9, &actualRate) FAILS.
    The error log is as follows:

[DEBUG] Using: fdiv = 26, Ndiv = 52.000000, fvco = 2600.000000 MHz
[DEBUG] fdiv = 26, Ndiv = 52.000000, Nint = 52, Nfrac = 0, fvco = 2600.000000 MHz
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=0, lo=0
[DEBUG] i=4, hi=0, lo=0
[DEBUG] i=3, hi=0, lo=0
[DEBUG] i=2, hi=0, lo=0
[DEBUG] i=1, hi=0, lo=0
[DEBUG] i=0, hi=0, lo=0
[DEBUG] lowest CSW_VCO 128, highest CSW_VCO 127
[DEBUG] i=6, hi=0, lo=0
[DEBUG] i=5, hi=1, lo=1
[DEBUG] i=4, hi=1, lo=1
[DEBUG] i=3, hi=1, lo=0
[DEBUG] i=2, hi=1, lo=0
[DEBUG] i=1, hi=1, lo=0
[DEBUG] i=0, hi=1, lo=0
[DEBUG] lowest CSW_VCO 200, highest CSW_VCO 207
[DEBUG] lowest CSW_VCO 200, highest CSW_VCO 207, CSW_VCO 203
[DEBUG] VCO OK
Return from LMS7002M_cgen.c:0Return value:0
Actual frequency rate:100000000.000000
[INFO] SXX tune 100.000000 MHz (fref=50.000000 MHz) begin
[DEBUG] fdiv = 2, Ndiv = 4.000000, fvco = 200.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 8.000000, fvco = 400.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 16.000000, fvco = 800.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 32.000000, fvco = 1600.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 64.000000, fvco = 3200.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 128.000000, fvco = 6400.000000 MHz
[DEBUG] fdiv = 128, Ndiv = 256.000000, fvco = 12800.000000 MHz
[DEBUG] fdiv = 256, Ndiv = 512.000000, fvco = 25600.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 4.000000, fvco = 200.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 8.000000, fvco = 400.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 16.000000, fvco = 800.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 32.000000, fvco = 1600.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 64.000000, fvco = 3200.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 128.000000, fvco = 6400.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 128.000000, fvco = 6400.000000 MHz
[DEBUG] fdiv = 2, Ndiv = 4.000000, fvco = 200.000000 MHz
[DEBUG] fdiv = 4, Ndiv = 8.000000, fvco = 400.000000 MHz
[DEBUG] fdiv = 8, Ndiv = 16.000000, fvco = 800.000000 MHz
[DEBUG] fdiv = 16, Ndiv = 32.000000, fvco = 1600.000000 MHz
[DEBUG] fdiv = 32, Ndiv = 64.000000, fvco = 3200.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 128.000000, fvco = 6400.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 128.000000, fvco = 6400.000000 MHz
[DEBUG] fdiv = 64, Ndiv = 64.000000, Nint = 60, Nfrac = 0, DIV_LOCH_SX = 5, fvco = 6400.000000 MHz
[DEBUG] Testing for SEL_VCO = 1
[DEBUG] VCO select FAIL - too low

VCO select FAIL -too low
[DEBUG] fdiv = 64, Ndiv = 64.000000, Nint = 60, Nfrac = 0, DIV_LOCH_SX = 5, fvco = 6400.000000 MHz
[DEBUG] Testing for SEL_VCO = 2
[DEBUG] VCO select FAIL - too low

VCO select FAIL -too low
-3 - Actual TX LO freq 100.000000 MHz

Thank you again for your time.

4

Regarding item (4):

  1. Set configuration (SISO, MIMO);
  2. Set interface settings: Configure LimeLight ports -> Set decimation/interpolation settings in Rx/Tx TSPs -> Configure CLKGEN (VCO cal)-> Configure CMIX -> Configure GFIRs
    Transmitter:
    Configure TX PLL (VCO cal)-> Configure LPF bandwidth (TX LPF cal) -> Configure Gain (TX gain cal) -> Configure output band -> Configure output power level -> Calibrate DC/LO (TX DC/LO cal) -> Calibrate IQ imbalance (TX IQ cal)
    Receiver:
    Configure RX PLL (if FDD is used, VCO cal)) -> Configure input band -> Configure gain -> Configure LPF bandwidth (RX LPF cal)-> Calibrate DC (RX DC cal) -> Calibrate IQ imbalance (RX IQ cal)

This is very rough procedure. A more detailed document describing these functions and procedures needed to setup LMS7002M will be published at the beginning of May.

7

Hello Zack,
The issues mentioned earlier have been resolved. The sequence of tests mentioned in access_test.c were run and the following were completed successfully:

  1. Setting CGEN
  2. Tx LO
  3. Rx LO
  4. TBB filter for both chA and chB
  5. RBB filter for both chA and chB

Out of the settings that you mentioned, the following are yet to be done:

  1. CMIX and GFIRs (this is purely digital so I suppose there is no need to worry about them for validating the hardware)
    Tx:
  2. Tx gain cal has to be done.
  3. What does configuring output band mean? (LO is set)
  4. Configure output power level: (is this setting the gains in the Tx path of the analog amplifiers)
  5. Calibrate DC/LO: Can this only be done and verified when the RF output is monitored on a spectrum analyzer?
  6. IQ imbalance: Again only by monitoring on a spectrum analyzer?

Rx:
7) Configuring band?
8) Receive path gains
9) Rx dc and IQ imbalance cal. Does an external signal have to be injected?

The document which you mentioned being released in early May, will it be sent by email or would a downloadable link be available (where?).

Thanks again,

8

Hi @EnthuMan,

Refer to this resource for more information:
https://wiki.myriadrf.org/LMS7002Mr3_Calibration_Using_MCU

LMS7002M got three RF inputs and two RF outputs - we call them bands. So, you have to configure which RF input/output (aka band) you want to use.

I will post a link to wiki. Just ping me end of next week, please.

I would suggest to check LimeSuite source code as well.

9

Hi Zack,
1) For the same settings (LO frequencies, filter bandwidths, gains, dc offset, IQ imbalance etc…) does the IC have to be calibrated everytime it is powercycled?
2) If not how can the settings be stored and re-applied?
3) How does this calibration hold against temperature variation?
4) Is the best way of choosing a setting (eg CSW for VCO) is to choose the center value of the successfully calibrated range?
5) What is the best way to synchronize multiple ICs? (phase synchronous outputs on RF Tx outs and same on digitized Rx ins)? Is providing the same xoscin_rx/tx sufficient?
6) The TSPs will have to be synchronized (since they are digital) along with the FIFOs in-between. How can that be taken of?
Apologies for flooding you with these questions but thank you for your time in advance.

10

Hi @Zack,
We are now planning to do the RxTSG test to verify the interface between the LMS chip and FPGA.
Could you please advise which are the registers to be configured to implement this (starting from CGEN, port configurations, data modes etc…).
In an other post, Rx signal capture using LMS7002
you had mentioned that
1. You can not set HBD/HBI to bypass. It should be 2^1. Otherwise MCLK frequency is not correct. This is very important!
may I ask you to please elaborate.

Also, there are still two more days but may I ask if the document you mentioned is ready?
Regards,

11

Hello @Zack,
Looking forward to your inputs and the document.
Regards,

12

Hi @EnthuMan,

Assuming RF2BB data direction. LML interface MCLK clock is derived from CGEN, which is the same for ADCs and RxTSPs. So, there are 4 ADCs and they generate 4 IQ data samples every clock cycle. Actually, there are 4 parallel buses coming to LML module for transmitting them to outside world. But there is only one clock line and only one IQ data bus. Hence we can transfer only 2 IQ data samples every clock cycle when using DDR, but we have 4 samples! Decimation helps to solve this issue. When we decimate by 2 at least, then we have one spare clock cycle at the interface meaning we can transfer 4 IQ data samples in 2 interface clock cycles using DDR.

14

Hello @Zack,
Things are progressing here. We were able to get the RxTSG flow working. The next step in our plan is to verify the FPGA to LMS interface DIQ1. For the same we found the LMS7002M_setup_digital_loopback in the driver api. However we are a little unclear about the clock settings. May I ask you to please advise.
Also, we are looking forward to your document.
Regards,

15

Hello @Zack,
Please advise on the register and clock settings for digital loopback.
Regards,

16

Hi @EnthuMan,

To loopback LML1 to LML2:

  1. Starting from default settings.
  2. You have to provide FCLK1 clock, derived from MCLK1; FCLK2 clock, derived from MCLK2.
  3. Set RX_MUX (0x002A[11:10]) to 01b.
  4. Set RXWRCLK_MUX (0x002A[1:0]) to 00b.
17

Hello @Zack,
In our board we do not have MCLK1 and FCLK2 connected between the LMS and FPGA.
Please advise if we can use some alternate setting,
Regards,

18

Hello @Zack,
Looking forward to your help.

19

Hello @Zack,
Two questions:

  1. Our RxTSG setup was working fine so far. Since two days what we are observing is that samples from channel B are all zero. What could cause this? (the FPGA code is the same).
  2. Please advise on the digital loop back setup.
    Regards,
20

OK, then just forget step (2) from setup list. Everything else should be the same.

Channel B RxTSP settings? ADC settings?

21

Channel B RxTSP settings? ADC settings?

Our sequence is as follows:

  1. set_data_clock
  2. configure_lml_port(lms,2,LMS_RX,1);
  3. reset_lml_fifo
  4. rxtsp_enable(lms, LMS_CHA,1);
  5. rxtsp_enable(lms,LMS_CHB,1);
  6. rxtsp_tsg_const(lms,LMS_CHA,…)
  7. rxtsg_tsg_const(lms,LMS_CHB,…)

Are we missing something, or are the names incorrect?

22

Not sure what these functions do, but I would suggest to reset LMS7002M using external dedicated pin after power on. Another thought - GFIRs are enabled by default after reset and may multiply your data by 0 if not configured. I would suggest to bypass GFIRs as well as AGC.

23

Hello @Zack,
The functions are from the generic driver provided on git.
Just double checked, the LMS reset is being applied. I am not sure if GFIRs and AGC would have an affect only on Channel B (the same settings are applicable to both channels A and B). Am I correct? Channel A seems perfectly normal at least for constant. May I also ask if you to please provide the waveform TSG is set to NCO.
Another strange thing that has arisen: changing the TSG full scale control doesn’t change the level.
These are things that have started happening recently and I quite clueless about this development.
Third point: HBDs are bypassed.
Let’s say
CGEN is set @ 200MHz.
ADC and RxTSP clock will then be 50MHz.
When set to TSG, NCO in TSG generates RxTSP Clk/8 tone (sampled at RxTSP Clk?). So in this case 50MSps.
Normally the relation between MCLK2 and DIQ2 data rate is 1:2 (i.e., DIQ2 is @ twice the rate of MCLK2). However, if HBD is bypassed then both the channels give out 50MSps x 4 = 200MSps which four times MCLK.
Something seems wrong with my calculation… may I ask you to please help clear the confusion.