Single tone generator test + sequence for other tests

Hi @EnthuMan,

LimeSuite is actively maintained at the moment only. Other drivers may work as well, but you have to pay attention and know what you are doing.

A and B channels are configured separately. Pay attention to MAC[1:0] register, which selects what channel is being configured. If you configure channel A only, then channel B is not configured.
As I wrote, GFIRs are enabled after reset is applied. If you do not bypass them explicitly, then it cancels your IQ data.

It generates four or eight 12 bit samples (depending on settings) per sine wave period.

Make sure AGC is bypass.

OK

Tone frequency will be Ftxtsp / 8 (or 4) / DecimatioRatio. If TSGFCW[1:0] = 01b, TSGMODE = 0, INSEL = 1, HBD_OVR[2:0] = 000b (i.e. decimation by 2), then tone frequency generated by RxTSG will be 50/8/2 = 3.125MHz. Sample rate of this tone will be 25MHz, not 50 (decimation by 2, remember?).

Correct.

This is a special case, which requires external clock signal, which is 2 times MCLK. There is no possibility to generate this frequency on LMS7002M. Let me explain why. MCLK is constructed from R(T)xTSP clock, i.e. R(T)xTSP clock is supplied directly to MCLK or after divider. Hence, when decimation is bypass, MCLK frequency must be twice of R(T)xTSP clock frequency (for instance: if ADC and RxTSP clock is 50MHz, decimation is bypass, 2x2 MIMO mode, then MCLK frequency must be 100MHz. But we can not get 100MHz out of 50MHz inside of LMS7002M, while there is no clock multiplier functionality. Hence the only option is to take MCLK as a reference clock for external PLL, multiply it by 2 and feed it back as FCLK. Check interface settings document for more information).

Hope this helps.

Hello @Zack,
May I ask if the startup (sequence) document is ready.
Regards,

Hi @EnthuMan,

The assigned person is occupied with other work currently hence document creation work was slowed down. Will update as soon as document is finished, sorry for inconvenience.