LMS6002 - What is "ADC sampling phase" parameter means?

System Development
1

Hi guys.
I have a stupid question: what “ADC sampling phase” parameter means?
Switching this bit (rising/falling edge) does not provide any changes on digital ADC interface, but it have critical effect in signal - for example, on rising edge i receive good constellation, and when i switch to falling edge then i result in crashed constellation.
I’m so confused - what is this? Datasheet does not answer to this, it just give this bit as fact…
Thanks.

UPD: i mean 0x5A register, bit RX_CTRL3[7].

2

Hi @ilkz,

This parameter controls ADC sampling clock polarity. Of course you will mess up if select falling edge.

3

To be a bit more detailed - changing that will shift the phase of where the ADC samples by 180 degrees, or one-half sample time. If you are sampling at, say, 4 samples per symbol, that will shift sample time one-eighth of a symbol time.