Using DDR for one ADC channel

[gasparka]

LimeSDR-Mini has one active ADC, but the DDR interface is configured to send both channels.
For reference:

Dedicating the interface for the active ADC would increase useful sample rate into the FPGA by factor of 2.
I see that the sample mux can be configured to always take I/Q samples from channel A:

But i did not find information about the clocks. In order to make it work one would need to divide ‘WRTCLK’ by 4 instead of 2 (automatically set by decimation block?), also the ‘READCLK’ needs to be divided by ‘2’.

Is this possible or am i dreaming?

[Zack]

Hi @gasparka,

@gasparka

LimeSDR-Mini has one active ADC, but the DDR interface is configured to send both channels

Do not know why you saying this.

LML interface of LimeSDR-Mini is set to send channel A data only, while LML interface mode is SISO DDR. Decimation/interpolation blocks are bypassed in this case hence the sample rate at the interface is the same as at DAC/ADC.

[gasparka]

Hi @Zack, thanks for the answer.

To clarify, my setup is using 40M sample rate with decimation of 4, so ADC rate is 160M.
I have been digging into the gateware and see (using SignalTap) that LML sends the A and B channel i.e. i get correct IQ signals only if i sample at the ‘not ENABLE_IQ_SEL_N2’, which corresponds to the A channel. B channel gives constant IQ values of I: 0x7FF, Q: 0x800.

[Zack]

Hi @gasparka,

Could you send register settings ini file, please. Do you use LimeSuiteGUI to configure LMS7002M?

[gasparka]

@Zack here is the ini file:

https://gist.github.com/gasparka/840f7b8c9b911564cb12dc8f63da8883

I am using SoapySDR and have changed the LimeSuite to allow decimation for LimeSDR Mini:

fix LimeSDR-Mini oversampling

Everything else is untouched.

[gasparka]

Looks like the sisoDDR mode is not enabled in case of oversampling:

bool sisoDDR = (oversample <= 1 && tx_channels[0].cF_offset_nco == 0.0 && rx_channels[0].cF_offset_nco == 0.0);

@Zack, is it possible to have oversampling and sisoDDR?

[Zack]

Hi @gasparka,

@gasparka

is it possible to have oversampling and sisoDDR?

Yes, it is possible. But, as you rightly noticed, there is a strange requirement from software side
Checking it, thanks for note!

[gasparka]

Awesome , with this we can stream 80M of filtered bandwidth into the FPGA.

[Zack]

Hi @gasparka,

Issue is fixed in the one of latest LimeSuite commits.

[gasparka]

Quick fix and support. Thanks @Zack and everyone involved.