I use FPGA to sample the ADC data of LMS6002D, the rx_clk is 40.92, so the rx_IQ_sel is 20.46,which is below the max sample frequency 40MHz. but the sample data of ADC is wrong, see figure below.
when the rx_IQ_sel polartiy is high or low, the adc data must be holding. but I use fpga to sample the data, the adc data has changed when rx_IQ_sel polartiy is high or below.
what’s wrong with the adc? what’s wrong with the LMS6002D?