RX sampling clock phase shift in FPGA

According to the datasheet, IQ samples can be recovered by sampling on the MCLK edges:

I have tried sampling with various phase shifts (for example -90 deg). Result is unreliable, works for 40MHz input but fails for 10MHz. Feels like the required phase shift is somehow related to the sample rate.

As a sanity check, is it even possible to, reliably, sample the IQ interface with constant phase shift?
Looking at the gateware of LimeSDR-Mini reveals that the sampling clock is tuned in software, why is this neccesarry? Any documentation about this?