LimeSDR-XTRX Timing Violations

[joe]

Hello,

I’m working on a project to make the LimeSDR-XTRX a frequency translator.The final product will not have access to python/GNU Radio, so I’m taking the route of updating the firmware by trying to loop the Rx data from the RFIC into the Tx data path of the RFIC. I figure that way I can still use the LimeSuiteNG gui to control the Tx and Rx frequencies.

I’ve downloaded the repo and have run the “Generate_Project.tcl” file. Using Vivado 2022.1, I tried generating the bitstream and I failed timing. I want to make sure my base project is correct before I start tinkering with things. Has anyone else had this issue when trying to generate the bit file from Vivado? Below are some screenshots of various reports, I tried to attach them as text files but wasn’t able to.

I did come across this post, LimeSDR-USB Quartus 15.1 fails timing, but it for Quartus, a different device, and 4 years old.

Thank you,
Joe

[ricardas]

@joe

I’m taking the route of updating the firmware by trying to loop the Rx data from the RFIC into the Tx data path of the RFIC.

You don’t need to modify FPGA gateware for that. You can achieve it simply by redirecting Rx FIFO into Tx FIFO within the LMS7002M chip, by setting register 0x002A[9:8]TXMUX to 2

[joe]

Awesome, thanks. I haven’t gotten my boards to play around with yet, so I didn’t realize that was an option. Are you using Lime Suite NG for that, or is there a different gui I need? Thanks again!

[ricardas]

Yes, that was a screenshot from LimeSuiteNG’s limeGUI.

[andrewback]

Just to add also that we’ve switched to a new unified LiteX-based gateware platform and so should you ever need to modify the gateware, this project should be used:

Introduction — LimeSDR FPGA Gateware (LimeSDR_GW) 24.09 documentation