LimeSDR-USB Quartus 15.1 fails timing

Hello,

I am working on making a few changes to the LimeSDR-USB gateware from the following repo.

GitHub - myriadrf/LimeSDR-USB_GW: Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

I have been able to clone the repo, open the project in quartus 15.1.2 Build 193 02/01/2016 SJ Lite (i.e lms7_trx.qpf), and compile. I have not made any gateware changes yet, so it should be the base fpga code, but seem to be failing timing already. Each model Slow 1200mV 85C, Fast 0C, slow 0C, have issues making timing.

I will say I come from the Xilinx world, so am learning the specifics of Quartus, but I would image that the base example shouldn’t fail timing? Is there something I am missing here or that someone would recommend?

Thanks

1 Like

Tagging @Zack.

Hi @space,

Have you tried to open the project using another version of Quartus before?
Check this: LimeSDR USB gateware Quartus problem

@Zack,

Thanks for getting back. Just to be sure I cloned a fresh copy and tried again but still got timing errors.

I added the build log to google drive if you want to take a look. https://drive.google.com/file/d/15bx8jd6CjZqsc2DTIL9ZlsfFTRdh9rqp/view?usp=sharing

In the fast configuration, I meet the setup timing but not the hold time or recovery time.

Ill just make a couple notes,

Even though the build has timing errors, it seems that the LimeSDR is still operating with correctly. Passing self tests, producing RF when data is sent. Still makes me nervous to continue but so far it has been alright.

My question would be, when you guys build it, do you (or anyone in the community) get timing errors or is it just me?

I downloaded and installed Quartus Prime Lite Edition Version 15.1.0 Build 185, with Cyclone IV device support and then installed the update to patch it to 15.1.2 Build 193. I then downloaded and extracted the zip file for the “LimeSDR-USB_GW” master branch from github. Double clicked on “lms7_trx.qpf” and ran a compile and got the same timing messages as you showed in the image in your original post highlighted in red.

I just assumed that it was because there are three fundamental clock sources on the LimeSDR-USB board: XO2 (VCTCXO 30.72MHz ±1 ppm initial; ±4 ppm stable - mostly used by LMS7002M ), XT1 (19.2MHz ±30ppm - FX3 probably needed for DFU mode, I’m not sure I’ve not looked into it at all) and XT2 (25MHz ±20ppm which is fed into a clock generator, Si5351C, to provide timing almost everywhere else that is digital) and that the human designers knew more than the Quartus Prime software at least when it came to timing in their design. (ref: https://wiki.myriadrf.org/LimeSDR-USB_hardware_description#Clock_distribution ; the schematic and Bill Of Materials). I did not bother to look into it at all, because I felt that I would need to fully understand the datasheet for the EZ-USB FX3, the EP4CE40F23C8N FPGA, the public document of the registers in the LMS7002M chip and I’d also need to read and fully understand all the gateware code. And learn my way around Quartus Prime a bit better than I currently do. At least one of the signals, to me anyhow, looks like it may be unused outside the FPGA FX3_PCLK_VIRT_OUT, but like I’ve said I’ve not looked into it at all.

@mzs,

Thanks for the answer, its relieving to know it wasn’t just me. Yeah I think your assumptions are most likely correct and the designers didnt feel the need to constraint certain clock or something like that. Ill be digging around the design so if I change anything that fixes timing issues Ill try to put a post about it.