LimeSDR XTRX RF Test failure

Hi everyone,

I’m having the following error when using limeOEM --test:

pi@cm4-dev bin % ./limeOEM --test
Board serial number: 0 (0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 )
=== LimeSDR-XTRX OEM Test ===
  === PCIe Reference clock ===
    results: 19109; 20671; 22233
  === PCIe Reference clock - PASSED ===

  === VCTCXO ===
    Count : 2606143 (min); 2606172 (max)
  === VCTCXO - PASSED ===

  === GNSS ===
  === GNSS - PASSED ===

  === LMS7002M ===
    Registers test
    Registers test PASSED
    External Reset line test
      Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
      Reg 0x20: value after reset 0x0FFFF
  === LMS7002M - PASSED ===

  === RF ===
    ->Configure LMS
    ->Init Done
    === TX_2->LNA_L ChA ===
    === TX_2->LNA_L ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-58.09 dbFS @30.720MHz)) ===

    === TX_2->LNA_L ChB ===
terminate called without an active exception
zsh: abort      ./limeOEM --test

Using LimeSuiteNG at Git hash 8a5cfc6bdb, and CM4 IO board as a host system with dtoverlay=pcie-32bit-dma overlay. The firmware of XTRX is the one it came with from CrowdSupply.

Is it a mismatch of firmware and software? Shall I try flashing an update? Or is the error is caused by something else?

The full device information:

pi@cm4-dev bin % ./limeDevice --full
Found 1 device(s) :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000
	Expansion name		: UNSUPPORTED
	Firmware version	: 1
	Gateware version	: 1
	Gateware revision	: 8
	Gateware target board	: LimeSDR XTRX
	Hardware version	: 0
	Protocol version	: 1
	Serial number		: 0
	SPI slave devices	:
				  FPGA
				  LMS7002M
	Memory devices		:
				  FPGA FLASH
	GPS Lock:
		GPS - Undefined
		Glonass - Undefined
		Galileo - Undefined
		Beidou - Undefined

If it is a matter of firmware update, maybe someone can confirm the proper file an command for it? Would be good to avoid JTAG recovery if possible :slight_smile:

P.S. The actual reason I’ve started looking into the self-test is because so far I hasn’t been able to see a signal from samples received from the XTRX. The data from XTRX is streaming, you can see a peak in FFT at the LO, but the rest is as if antenna is not attached and you’re looking at a noise floor.

Tagging @ricardas.

I’ve fixed the exception error.
The test expects external loopback, so that Tx would be connected to Rx using 20dBm attenuator.

Hi, thanks for the quick fix!

I am a bit confused about the 20dBm attenuator. If I put 20dB (and I’ve double-checked it is -20dB LOGMAG S21) attenuator between TxB and RxA I get

    === TX_2->LNA_L ChA ===
    === TX_2->LNA_L ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-21.18 dbFS @5.003MHz)) ===

If I use 10dB attenuator then the test passes:

    === TX_2->LNA_L ChA ===
      RF OK, expected(-8.00 dbFS @ 5.000MHz), got(-11.89 dbFS @5.003MHz)
    === TX_2->LNA_L ChA - PASSED ===

P.S. What do you think of adding a note in the test program about possibly missing external feedback (maybe when all measured signal strength are below some threshold)?

The loopback should be between each channels Tx Rx. That is TxA->RxA, TxB->RxB.

TX_2->LNA_L ChA means TxA Band2 → RxA LNA_L

Ah, I see, i was a bit confused. Thanks for the clarification! Will give it another test.
And just to confirm, it should be 20dB attenuation (TxA -> 20dB attenuator -> RxA)?

Correct, same for channel B too.

Unfortunately, the tests are still failing. Using the LimeSuiteNG rev d53f1085a7e:

Board serial number: 0 (0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 )
=== LimeSDR-XTRX OEM Test ===
  === PCIe Reference clock ===
    results: 26299; 27861; 29423
  === PCIe Reference clock - PASSED ===

  === VCTCXO ===
    Count : 2606144 (min); 2606172 (max)
  === VCTCXO - PASSED ===

  === GNSS ===
  === GNSS - PASSED ===

  === LMS7002M ===
    Registers test
    Registers test PASSED
    External Reset line test
      Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
      Reg 0x20: value after reset 0x0FFFF
  === LMS7002M - PASSED ===

  === RF ===
    ->Configure LMS
    ->Init Done
    === TX_2->LNA_L ChA ===
    === TX_2->LNA_L ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-20.15 dbFS @5.003MHz)) ===

    === TX_2->LNA_L ChB ===
    === TX_2->LNA_L ChB - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-21.43 dbFS @5.003MHz)) ===

    === TX_2->LNA_W ChA ===
    === TX_2->LNA_W ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-20.27 dbFS @5.003MHz)) ===

    === TX_2->LNA_W ChB ===
    === TX_2->LNA_W ChB - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-18.12 dbFS @5.003MHz)) ===

    === TX_1->LNA_H ChA ===
    === TX_1->LNA_H ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-29.50 dbFS @5.003MHz)) ===

    === TX_1->LNA_H ChB ===
    === TX_1->LNA_H ChB - FAILED (RF FAILED, expected(-15.00 dbFS @ 5.000MHz), got(-35.98 dbFS @5.003MHz)) ===

  === RF - FAILED ===

=== LimeSDR-XTRX OEM Test - FAILED ===

OEM TEST FAILED

Edit: The fuller debug log:

Board serial number: 0 (0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 )
=== LimeSDR-XTRX OEM Test ===
  === PCIe Reference clock ===
    results: 16121; 17683; 19245
  === PCIe Reference clock - PASSED ===

  === VCTCXO ===
    Count : 2606140 (min); 2606169 (max)
  === VCTCXO - PASSED ===

  === GNSS ===
  === GNSS - FAILED (timeout) ===

  === LMS7002M ===
    Registers test
    Registers test PASSED
    External Reset line test
      Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
      Reg 0x20: value after reset 0x0FFFF
  === LMS7002M - PASSED ===

  === RF ===
    ->Configure LMS
    ->Init Done
Set Rx LO frequency (1000 MHz)
VCOH skipped
SX VCO:4000.000 MHz, RefClk:26.000 MHz, INT:149, FRAC:887256, DIV_LOCH:1, EN_DIV2_DIVPROG:0
Tuning Rx VCOL (ICT_VCO:255):
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64	cmphl=3
csw=32	cmphl=0
csw=48	cmphl=2
csw=56	cmphl=3
csw=52	cmphl=2
csw=54	cmphl=3
csw=53	cmphl=2
adjust with linear search:
csw=47	cmphl=0
CSW: lowest=48, highest=53, will use=50
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=3
csw=132	cmphl=3
csw=130	cmphl=3
csw=129	cmphl=3
adjust with linear search:
CSW interval failed to lock
choosing wider CSW locking range: low=48, high=53
TuneVCO(SXR) - confirmed lock with final csw=50, cmphl=2
VCOL : csw=50 tune ok
Selected: VCOL, CSW_VCO: 50
Set Tx LO frequency (1005 MHz)
VCOH skipped
SX VCO:4020.000 MHz, RefClk:26.000 MHz, INT:150, FRAC:645277, DIV_LOCH:1, EN_DIV2_DIVPROG:0
Tuning Tx VCOL (ICT_VCO:255):
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64	cmphl=3
csw=32	cmphl=0
csw=48	cmphl=0
csw=56	cmphl=2
csw=60	cmphl=3
csw=58	cmphl=3
csw=57	cmphl=3
adjust with linear search:
csw=55	cmphl=2
csw=54	cmphl=2
csw=53	cmphl=2
csw=52	cmphl=2
csw=51	cmphl=0
CSW: lowest=52, highest=56, will use=54
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=3
csw=132	cmphl=3
csw=130	cmphl=3
csw=129	cmphl=3
adjust with linear search:
CSW interval failed to lock
choosing wider CSW locking range: low=52, high=56
TuneVCO(SXT) - confirmed lock with final csw=54, cmphl=2
VCOL : csw=54 tune ok
Selected: VCOL, CSW_VCO: 54
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
RxLPF modifying G_PGA_RBB 0 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
RxLPF modifying G_PGA_RBB 0 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
Sampling rate set(61.440 MHz): CGEN:491.520 MHz, Decim: 2^1, Interp: 2^1
INT 74, FRAC 648503, DIV_OUTCH_CGEN 1
VCO 1966.08 MHz, RefClk 26.00 MHz
FPGA::SetInterfaceFreq tx:122.880 MHz rx:122.880 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 1
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 1
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
    === TX_2->LNA_L ChA ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 38
    === TX_2->LNA_L ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-17.90 dbFS @5.003MHz)) ===

    === TX_2->LNA_L ChB ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 78
    === TX_2->LNA_L ChB - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-19.22 dbFS @5.003MHz)) ===

Set Rx LO frequency (2000 MHz)
VCOH skipped
SX VCO:4000.000 MHz, RefClk:26.000 MHz, INT:149, FRAC:887256, DIV_LOCH:0, EN_DIV2_DIVPROG:0
Tuning Rx VCOL (ICT_VCO:255):
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64	cmphl=3
csw=32	cmphl=0
csw=48	cmphl=2
csw=56	cmphl=3
csw=52	cmphl=2
csw=54	cmphl=3
csw=53	cmphl=2
adjust with linear search:
csw=47	cmphl=0
CSW: lowest=48, highest=53, will use=50
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=3
csw=132	cmphl=3
csw=130	cmphl=3
csw=129	cmphl=3
adjust with linear search:
CSW interval failed to lock
choosing wider CSW locking range: low=48, high=53
TuneVCO(SXR) - confirmed lock with final csw=50, cmphl=2
VCOL : csw=50 tune ok
Selected: VCOL, CSW_VCO: 50
Set Tx LO frequency (2005 MHz)
VCOH skipped
SX VCO:4010.000 MHz, RefClk:26.000 MHz, INT:150, FRAC:241979, DIV_LOCH:0, EN_DIV2_DIVPROG:0
Tuning Tx VCOL (ICT_VCO:255):
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64	cmphl=3
csw=32	cmphl=0
csw=48	cmphl=0
csw=56	cmphl=3
csw=52	cmphl=2
csw=54	cmphl=2
csw=55	cmphl=2
adjust with linear search:
csw=51	cmphl=2
csw=50	cmphl=2
csw=49	cmphl=2
csw=48	cmphl=0
CSW: lowest=49, highest=55, will use=52
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=3
csw=132	cmphl=3
csw=130	cmphl=3
csw=129	cmphl=3
adjust with linear search:
CSW interval failed to lock
choosing wider CSW locking range: low=49, high=55
TuneVCO(SXT) - confirmed lock with final csw=52, cmphl=2
VCOL : csw=52 tune ok
Selected: VCOL, CSW_VCO: 52
RxLPF modifying G_PGA_RBB 0 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
RxLPF modifying G_PGA_RBB 0 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
Sampling rate set(61.440 MHz): CGEN:491.520 MHz, Decim: 2^1, Interp: 2^1
INT 74, FRAC 648503, DIV_OUTCH_CGEN 1
VCO 1966.08 MHz, RefClk 26.00 MHz
FPGA::SetInterfaceFreq tx:122.880 MHz rx:122.880 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 1
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 1
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
    === TX_2->LNA_W ChA ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 118
    === TX_2->LNA_W ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-17.11 dbFS @5.003MHz)) ===

    === TX_2->LNA_W ChB ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 158
    === TX_2->LNA_W ChB - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-15.03 dbFS @5.003MHz)) ===

Set Rx LO frequency (3500 MHz)
SX VCO:7000.000 MHz, RefClk:26.000 MHz, INT:130, FRAC:645277, DIV_LOCH:0, EN_DIV2_DIVPROG:1
Tuning Rx VCOH (ICT_VCO:255):
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64	cmphl=0
csw=96	cmphl=0
csw=112	cmphl=0
csw=120	cmphl=2
csw=124	cmphl=2
csw=126	cmphl=2
csw=127	cmphl=2
adjust with linear search:
csw=119	cmphl=2
csw=118	cmphl=0
CSW: lowest=119, highest=127, will use=123
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=2
csw=140	cmphl=2
csw=142	cmphl=3
csw=141	cmphl=2
adjust with linear search:
csw=135	cmphl=2
csw=134	cmphl=2
csw=133	cmphl=2
csw=132	cmphl=2
csw=131	cmphl=2
csw=130	cmphl=2
csw=129	cmphl=2
csw=128	cmphl=2
CSW: lowest=128, highest=141, will use=134
CSW is locking in one continuous range: low=119, high=141
TuneVCO(SXR) - confirmed lock with final csw=130, cmphl=2
VCOH : csw=130 tune ok
Selected: VCOH, CSW_VCO: 130
Set Tx LO frequency (3505 MHz)
SX VCO:7010.000 MHz, RefClk:26.000 MHz, INT:130, FRAC:846926, DIV_LOCH:0, EN_DIV2_DIVPROG:1
Tuning Tx VCOH (ICT_VCO:255):
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64	cmphl=0
csw=96	cmphl=0
csw=112	cmphl=0
csw=120	cmphl=2
csw=124	cmphl=2
csw=126	cmphl=2
csw=127	cmphl=2
adjust with linear search:
csw=119	cmphl=0
CSW: lowest=120, highest=127, will use=123
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192	cmphl=3
csw=160	cmphl=3
csw=144	cmphl=3
csw=136	cmphl=2
csw=140	cmphl=2
csw=142	cmphl=2
csw=143	cmphl=3
adjust with linear search:
csw=135	cmphl=2
csw=134	cmphl=2
csw=133	cmphl=2
csw=132	cmphl=2
csw=131	cmphl=2
csw=130	cmphl=2
csw=129	cmphl=2
csw=128	cmphl=2
CSW: lowest=128, highest=142, will use=135
CSW is locking in one continuous range: low=120, high=142
TuneVCO(SXT) - confirmed lock with final csw=131, cmphl=2
VCOH : csw=131 tune ok
Selected: VCOH, CSW_VCO: 131
RxLPF modifying G_PGA_RBB 8 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
RxLPF modifying G_PGA_RBB 8 -> 12
RxLPF(0): TIA_C=4095, TIA_RCOMP=15, TIA_CCOMP=15, RX_L_C=2047, RX_H_C=255

RxLPF bypassed
TxLPF bypassed
Sampling rate set(61.440 MHz): CGEN:491.520 MHz, Decim: 2^1, Interp: 2^1
INT 74, FRAC 648503, DIV_OUTCH_CGEN 1
VCO 1966.08 MHz, RefClk 26.00 MHz
FPGA::SetInterfaceFreq tx:122.880 MHz rx:122.880 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 1
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 1
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
    === TX_1->LNA_H ChA ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 190
    === TX_1->LNA_H ChA - FAILED (RF FAILED, expected(-8.00 dbFS @ 5.000MHz), got(-26.16 dbFS @5.003MHz)) ===

    === TX_1->LNA_H ChB ===
FPGA: StopStreaming
FPGA: StopWaveformPlayback
FPGA: ResetPacketCounters
FPGA: ResetTimestamp
Rx0 Setup: usePoll:1 rxSamplesInPkt:1020 rxPacketsInBatch:2, DMA_ReadSize:7968

SetOSThreadPriority: Failed to set priority(6), schec_prio(2), policy(1), ret(99)
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
FPGA: StartStreaming
FPGA: StopStreaming
Rx0: packetsIn: 222
    === TX_1->LNA_H ChB - FAILED (RF FAILED, expected(-15.00 dbFS @ 5.000MHz), got(-32.72 dbFS @5.003MHz)) ===

  === RF - FAILED ===

=== LimeSDR-XTRX OEM Test - FAILED ===

OEM TEST FAILED
Tx0 stop: host sent packets: 0 (0x00000000), FPGA packet ingresed: 0 (0x00000000), diff: 0, Tx packet dropped: 0
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3

Edit: I think I misunderstood how some of the tests are supposed to work. Please fast-forward to my next message. I’ll leave this message in its close-to-original form for the continuity of the discussion, for those who might have read it already.


Trying to nail down the issue with the tests on whether it is on Tx or Rx side. So i’ve connected both Tx channels of XTRX to a scope, into 1 MOhm input, 1:1 probe. Used LimeSuiteNG Git hash 6d93bc06943.

Using basicTX does not result in any signals appearing on the scope, despite the fact that no errors are printed, and the log messages TX total samples sent with the number of samples in increments of about 1e+7 appearing in the console.

Using legacy/basicTX results in signal appearing on the TxA, but it seems to be weirdly modulated at some weird frequencies:


Also, there are a lot of errors in the console about the wrong number of samples sent. For example, error: samples sent: 1536/8190, but usually it is 0 samples sent.

[only now i’ve noticed i forgot to capture it at 1000ns time scale, but hopefully the current captures are enough to get an idea]

I’ve also tried to see what happens on the Tx channels when using limeOEM --test. The observations are:

  • Transmission starts at both Tx channels
  • The transmission is also modulatd



So definitely something odd is going on with the Tx, which is why the RF Test is failing. But I am not sure what the next steps could be.

I did a deeper dig into the code, and turns out I misunderstood how some of the tests are supposed to work.

The legacy/basicTX is actually supposed to do some form of modulation, around 500MHz center frequency, with 1MHz tone. And the carrier is confirmed to be at 500MHz by the scope measurements.

The limeOEM --test I can not really measure with my scope, as it uses 1GHz and above of the center frequency, and that is beyond of what my scope can do. So can not trust those pictures.
Same goes to the attenuator I use. They are pretty flat -20dB up to about 1400MHz, but 2GHz and above is probably beyond of what they are rated for.

When it comes to the original topic of limeOEM --test, I am not sure why TX_2->LNA_L fails, as that should be within the specs of my attenuator and cabling. Maybe someone has clues about that?. The higher ranges I can not test with my current equipment, so will look into some upgrades. Will report back when there are updates.

Other observations:

  • Not sure if it is expected that both Tx channels are activated when doing limeOEM --test.
  • The packed drop with legacy/basicRX is an issue.
  • Using limeOEM --test after examples/basicTX results in CMD 56 Read timeout. Doing limeConfig -i solves the issue.

Shall i report the latter two to the Github repository?

You are using quite old gateware, this issue has been fixed Fix for PLL configuration hang · myriadrf/LimeSDR-XTRX_GW@1834a1d · GitHub

you can update the gateware using limeFLASH flash_programming_file.bin

Ah, that’s lovely!
Seems the files changed a few hours ago. Can you confirm that now it is this one to be flashed:

I haven’t tried the latest myself. I’m currently using this one LimeSDR-XTRX_GW/bitstream/flash_programming_file.bin at bdd0c69078e70f6bef4e2c8985771f7e9a65e249 · myriadrf/LimeSDR-XTRX_GW · GitHub

Thanks Ricardas!
Updated to that version of the gateware now.

I’d need to come back to the RF tests, after I get properly rated attenuators for the frequencies used by the tests.