LimeSDR Mini USB errors

Projects LimeSDR
1

I have a problem similar to the one described here: ERROR: TransferPacket: Write failed (ret=0) but mine isn’t solved by plugging directly into the computer.

This happened on a day when I was having strange USB port issues, possibly due to the cold temperature affecting the motherboard. My external hard drives were also randomly disconnecting at that time. When it happened, I was using the board to transmit nonstop QPSK at 903 MHz. Everything seems fine now and I’m able to use the mouse, keyboard, webcam, and 2 external hard drives but not the LimeSDR Mini anymore. Whatever happened is also preventing me from flashing the firmware so I’m wondering if I have to buy a USB blaster to fix it.

I made sure to install the latest FTDI driver, version 1.3.0.4. I also tried it on another computer with USB 2 and 3 just to make sure it wasn’t a problem with my USB ports. On this other computer I got a slightly different set of errors in LimeSuite that said, “ERROR: TransferPacket: Read failed (64 bytes)”.

Here are my LimeQuickTest results:

C:\Windows\system32>limequicktest
[ TESTING STARTED ]
->Start time: Wed Dec 23 11:31:03 2020

TransferPacket: Read failed (ret=-1)
TransferPacket: Read failed (ret=-1)
TransferPacket: Read failed (ret=-1)
TransferPacket: Read failed (ret=-1)
TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
Board not supported
Failed to connect

As you can see, it shows up in LimeSuite’s device list.

limemini_device_list
limemini_device_list426×261 1.5 KB

However, this is what LimeSuite reports when I try to connect to it:

[11:39:04] INFO: Disconnected control port
[11:40:55] ERROR: TransferPacket: Read failed (ret=-1) x3
[11:40:55] ERROR: TransferPacket: Write failed (ret=-1) x35
[11:40:59] INFO: Connected Control port: UNKNOWN FW:0 HW:0 Protocol:0 GW:0.0 Ref Clk: -0.00 MHz

2

It does look as though firmware may be corrupted. Is there another port or computer you can try though?

3

Yes, I tried it on another computer with USB 2 and 3 ports and made sure to try both types of ports and I got almost the same error in LimeSuite: “ERROR: TransferPacket: Read failed (64 bytes)”.

If the firmware is bad, how can I fix it?

4

@Zack, if you could take a look and advise, please.

5

Hello @hcb,

Yes, it looks like FPGA gateware was corrupted. USB Blaster should help in this case I think.

6

Thank you, @Zack. Is this what I should buy or do you recommend something else? https://www.amazon.com/RioRand-Blaster-CPLD-FPGA-programmer/dp/B00IRODADK

7

Hi @hcb,

Not sure about this. Search this forum, there was a discussion about it. I’ve tried it, but I couldn’t program LimeSD-Mini using this device. We were able to program other FPGA if I recall correctly
I would go with this:
https://www.digikey.com/en/products/detail/terasic-inc/P0302/2003484
This will definitely work (we use these programmers in our lab).

8

This clone from Amazon was able to fix one of my SDR’s but the other one is still broken which makes me think it was somehow physically messed up. The only visible issue is that I accidentally flexed the USB port a little, but since it shows up normally in Device Manager and LimeSuite GUI’s connection dialog I don’t think that’s the problem.

When I plug in the one I was able to fix, it flashes red and yellow. The one that’s still broken does the same for a while but it sometimes stops on either red or yellow and then resumes the alternating pattern.

I also noticed that the lights now turn off completely on the fixed one when I stop transmitting but since it transmits properly I think it might just be how the new gateware works.

bent_usb
bent_usb923×433 92.2 KB

9

My second SDR just failed again and for some reason I can’t fix it this time. I also noticed that it’s giving a different set of errors compared to the first one. My computer’s USB ports failed again and stopped some downloads I was doing onto an external hard drive, which is what happened the first time the SDR’s broke.

I re-flashed both SDR’s today and tried them afterward and these are the errors I got.

limesdr_mini_2_different_errors
limesdr_mini_2_different_errors741×372 6.4 KB

I did a Google search and some LimeSDR users have had trouble when their USB ports didn’t provide enough power so I’m going to see if my SDR’s work on any other computers.

10

I just tested both SDR’s on my Raspberry Pi and the second one was able to transmit but the first one causes the same errors shown in the Windows screenshot for “SDR #1” along with a libusb warning saying “the application left some devices open”. For this test I powered the Raspberry Pi with a benchtop power supply set to 5.25 volts. I tested the SDR’s separately and their current (not counting the Pi) averaged 0.21 amps when they were first plugged in and, for the one that could transmit, 0.67 amps while transmitting. The average current used by the entire setup was 0.474 amps (2.49 watts) after the SDR was plugged in and 0.94 amps (4.94 watts) while transmitting.

This means the second SDR isn’t actually broken but since the first one still is, I think it might have a hardware issue.

11

Raspberry Pi is not a great choice if you are looking to rule out power supply issues. It should work and we have used RPi boards fine before, but the LimeSDR Mini is a USB 3.0 device and any RPi version prior to 4 is only USB 2.0. In addition to which an RPi itself can struggle if the power supply is not up to scratch. Hence would strongly recommend trying another desktop/laptop.

12

I just tested both SDR’s on a computer with USB 3.0 and the second one works but the first one still doesn’t. I made sure to re-flash the first one right before testing it, just in case using it with an underpowered USB 2.0 port is what messed it up. The errors for the first one are the same but I know it’s able to send data over the USB pins because LimeSuite and my console program recognize it.

13

OK. So I’m confused between which is which of the two boards. The one that is failing is the one with the bent USB connector, or has that one never worked since being damaged and do you mean the one that you previously reprogrammed with the USB Blaster?

14

"The one that is failing is the one with the bent USB connector" Yes
"or has that one never worked since being damaged" No, it continued to work from July 2019 (when I bent the connector) until late 2020.
"and do you mean the one that you previously reprogrammed with the USB Blaster?" I reprogrammed both of them so I’m not sure which one you’re referring to.

Board 1 has the bent USB connector. This happened around July 2019 and it continued to work until late 2020. Its serial number is 1D39984FFF88BF.

Board 2 is the one that was never physically messed up. I was able to fix it and use it on a desktop computer with USB 3.0 and a Raspberry Pi. Its serial number is 1D398F4769AE6A.

15

Hi @hcb

It looks like USB related part of the board still works even with connector was bent while it reads FTDI serial number successfully. It is obvious that there is no communication between FTDI and FPGA. Reasons may be:

  1. FPGA is still not programmed;
  2. It got some other issues which prevents FPGA operation;
  3. Interface between FTDI and FPGA issues.

Would try to program it using Altera programmer instead of this cheap thing you are using (although it works OK for the other board but I do not trust this kind of equipment).

16

same problem …

Hello dear colleagues

I have a big problem .

Today I wanted to make an update to SDR LIME mini v.1.3 and I broke it. Now he doesn’t see it as SDR just like this: “FTDI FT601 USB 3.0 Bridge device”

Please help me how I can rewrite all the firmware or enter DFU mode to reset the SDR to work again

with sdr Suite GUI does not work

Lime suit GUI also sees the serial and connects but it gives me an error message (I can also send the picture)

Please help me if possible.

Thank you very much

17

What I’ve tested so far:
-I have tetstat with 3 computers (with usb 2.0 and 3.0)
-It seems that the USB / serial converter works as it appears in the correct device manager, and at Lime Suite Gui it connects and the SDR serial appears.
If the LOG window appears: “Connected control port: Unknown FW: 0 HW: 4124992 Protocol: 0GW: 0.0 Ref Clk: -0.00MHz”

If you please help me with what software I can rewrite the firmware and possibly if you have the opportunity to explain step by step.
I downloaded several software but failed. there is a lot of information and I got confused: ((((
Thank you from the bottom of my heart for your help.

Lime sdr 3
Lime sdr 32048×945 122 KB

Lime sdr 2
Lime sdr 22048×945 203 KB

Lime sdr 1
Lime sdr 12048×945 138 KB

18

I think I have similar problem.
Using LimeSDR mini

PS C:\Program Files\PothosSDR\bin> .\LimeQuickTest.exe
[ TESTING STARTED ]
->Start time: Tue Nov 23 16:47:47 2021
->LimeSuite version: 20.10.0-PothosSDR-2021.07.25-vc16-x64

TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
TransferPacket: Write failed (ret=-1)
Board not supported
Failed to connect

PS C:\Program Files\PothosSDR\bin> .\limeutil --info
######################################################

LimeSuite information summary

######################################################

Version information:
Library version: v20.10.0-PothosSDR-2021.07.25-vc16-x64
Build timestamp: 2021-07-25
Interface version: v2020.10.0
Binary interface: 20.10-1

System resources:
Installation root: C:\Program Files\PothosSDR
User home directory:
App data directory: C:\Users\ct_lee\AppData\Roaming/LimeSuite
Config directory: /.limesuite
Image search paths:
- C:\Users\ct_lee\AppData\Roaming/LimeSuite/images
- C:\Program Files\PothosSDR/share/LimeSuite/images

Supported connections:

  • FT601
  • FX3
  • PCIEXillybus

PS C:\Program Files\PothosSDR\bin> .\SoapySDRUtil --probe=“driver=lime”
######################################################

Soapy SDR – the SDR abstraction library

######################################################

Probe device driver=lime
←[1m←[33m[WARNING] SoapyVOLKConverters: no VOLK config file found. Run volk_profile for best performance.←[0m
[INFO] Make connection: ‘LimeSDR Mini [USB 3] 1D4C2AF75EB323’
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
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[INFO] Device name: UNKNOWN
[INFO] Reference: -1e-06 MHz
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←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
[INFO] LMS7002M register cache: Disabled
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] SetFrequencyCGEN(61.44 MHz) failed←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
…

– Device identification

driver=FT601
hardware=UNKNOWN
boardSerialNumber=0xf75eb323
expansionName=UNKNOWN
firmwareVersion=0
gatewareVersion=0.0
hardwareVersion=0
protocolVersion=0

– Peripheral summary

Channels: 2 Rx, 2 Tx
Timestamps: YES
Sensors: clock_locked, lms7_temp
* clock_locked (Clock Locked): false
CGEN clock is locked, good VCO selection.
* lms7_temp (LMS7 Temperature): 0.000000 C
The temperature of the LMS7002M in degrees C.
Registers: BBIC, RFIC0
Other Settings:
* SAVE_CONFIG - Save LMS settings to file
[key=SAVE_CONFIG, type=string]
* LOAD_CONFIG - Load LMS settings from file
[key=LOAD_CONFIG, type=string]
* OVERSAMPLING - oversampling ratio (0 - auto)
[key=OVERSAMPLING, type=int, options=(0, 1, 2, 4, 8, 16, 32)]
GPIOs: MAIN

– RX Channel 0

Full-duplex: YES
Supports AGC: NO
Stream formats: CF32, CS12, CS16
Native format: CS16 [full-scale=32767]
Stream args:
* Buffer Length - The buffer transfer size over the link.
[key=bufferLength, units=samples, default=0, type=int]
* Link Format - The format of the samples over the link.
[key=linkFormat, default=CS16, type=string, options=(CS16, CS12)]
* Skip Calibration - Skip automatic activation calibration.
[key=skipCal, default=false, type=bool]
* align phase - Attempt to align phase of Rx channels.
[key=alignPhase, default=false, type=bool]
Antennas: NONE, LNAH, LNAL, LNAW, LB1, LB2
Corrections: DC removal, DC offset, IQ balance
Full gain range: [-12, 61] dB
TIA gain range: [0, 12] dB
LNA gain range: [0, 30] dB
PGA gain range: [-12, 19] dB
Full freq range: [0, 3800] MHz
RF freq range: [30, 3800] MHz
BB freq range: [6.25e-08, -6.25e-08] MHz
Tune args:
* LO Offset - Tune the LO with an offset and compensate with the baseband CORDIC.
[key=OFFSET, units=Hz, default=0.0, type=float]
* BB - Specify a specific value for this component or IGNORE to skip tuning it.
[key=BB, units=Hz, default=DEFAULT, type=float, options=(DEFAULT, IGNORE)]
Sample rates: [0.1, 61.44] MSps
Filter bandwidths: [1.4001, 130] MHz
Sensors: lo_locked
* lo_locked (LO Locked): false
LO synthesizer is locked, good VCO selection.
Other Settings:
* TSP_CONST - Digital DC test signal level in LMS7002M TSP chain.
[key=TSP_CONST, default=16383, type=int, range=[0, 32767]]
* CALIBRATE - DC/IQ calibration bandwidth
[key=CALIBRATE, type=float, range=[2.5e+06, 1.2e+08]]
* ENABLE_GFIR_LPF - LPF bandwidth (must be set after sample rate)
[key=ENABLE_GFIR_LPF, type=float]
* TSG_NCO - Enable NCO test signal
[key=TSG_NCO, default=4, type=int, options=(-1, 4, 8)]

– RX Channel 1

Full-duplex: YES
Supports AGC: NO
Stream formats: CF32, CS12, CS16
Native format: CS16 [full-scale=32767]
Stream args:
* Buffer Length - The buffer transfer size over the link.
[key=bufferLength, units=samples, default=0, type=int]
* Link Format - The format of the samples over the link.
[key=linkFormat, default=CS16, type=string, options=(CS16, CS12)]
* Skip Calibration - Skip automatic activation calibration.
[key=skipCal, default=false, type=bool]
* align phase - Attempt to align phase of Rx channels.
[key=alignPhase, default=false, type=bool]
Antennas: NONE, LNAH, LNAL, LNAW, LB1, LB2
Corrections: DC removal, DC offset, IQ balance
Full gain range: [-12, 61] dB
TIA gain range: [0, 12] dB
LNA gain range: [0, 30] dB
PGA gain range: [-12, 19] dB
Full freq range: [0, 3800] MHz
RF freq range: [30, 3800] MHz
BB freq range: [6.25e-08, -6.25e-08] MHz
Tune args:
* LO Offset - Tune the LO with an offset and compensate with the baseband CORDIC.
[key=OFFSET, units=Hz, default=0.0, type=float]
* BB - Specify a specific value for this component or IGNORE to skip tuning it.
[key=BB, units=Hz, default=DEFAULT, type=float, options=(DEFAULT, IGNORE)]
Sample rates: [0.1, 61.44] MSps
Filter bandwidths: [1.4001, 130] MHz
Sensors: lo_locked
* lo_locked (LO Locked): false
LO synthesizer is locked, good VCO selection.
Other Settings:
* TSP_CONST - Digital DC test signal level in LMS7002M TSP chain.
[key=TSP_CONST, default=16383, type=int, range=[0, 32767]]
* CALIBRATE - DC/IQ calibration bandwidth
[key=CALIBRATE, type=float, range=[2.5e+06, 1.2e+08]]
* ENABLE_GFIR_LPF - LPF bandwidth (must be set after sample rate)
[key=ENABLE_GFIR_LPF, type=float]
* TSG_NCO - Enable NCO test signal
[key=TSG_NCO, default=4, type=int, options=(-1, 4, 8)]

– TX Channel 0

Full-duplex: YES
Supports AGC: NO
Stream formats: CF32, CS12, CS16
Native format: CS16 [full-scale=32767]
Stream args:
* Buffer Length - The buffer transfer size over the link.
[key=bufferLength, units=samples, default=0, type=int]
* Link Format - The format of the samples over the link.
[key=linkFormat, default=CS16, type=string, options=(CS16, CS12)]
* Skip Calibration - Skip automatic activation calibration.
[key=skipCal, default=false, type=bool]
* align phase - Attempt to align phase of Rx channels.
[key=alignPhase, default=false, type=bool]
Antennas: NONE, BAND1, BAND2
Corrections: DC offset, IQ balance
Full gain range: [-12, 64] dB
PAD gain range: [0, 52] dB
IAMP gain range: [-12, 12] dB
Full freq range: [0, 3800] MHz
RF freq range: [30, 3800] MHz
BB freq range: [2.5e-07, -2.5e-07] MHz
Tune args:
* LO Offset - Tune the LO with an offset and compensate with the baseband CORDIC.
[key=OFFSET, units=Hz, default=0.0, type=float]
* BB - Specify a specific value for this component or IGNORE to skip tuning it.
[key=BB, units=Hz, default=DEFAULT, type=float, options=(DEFAULT, IGNORE)]
Sample rates: [0.1, 61.44] MSps
Filter bandwidths: [5, 40], [50, 130] MHz
Sensors: lo_locked
* lo_locked (LO Locked): false
LO synthesizer is locked, good VCO selection.
Other Settings:
* TSP_CONST - Digital DC test signal level in LMS7002M TSP chain.
[key=TSP_CONST, default=16383, type=int, range=[0, 32767]]
* CALIBRATE - DC/IQ calibration bandwidth
[key=CALIBRATE, type=float, range=[2.5e+06, 1.2e+08]]
* ENABLE_GFIR_LPF - LPF bandwidth (must be set after sample rate)
[key=ENABLE_GFIR_LPF, type=float]
* TSG_NCO - Enable NCO test signal
[key=TSG_NCO, default=4, type=int, options=(-1, 4, 8)]

– TX Channel 1

Full-duplex: YES
Supports AGC: NO
Stream formats: CF32, CS12, CS16
Native format: CS16 [full-scale=32767]
Stream args:
* Buffer Length - The buffer transfer size over the link.
[key=bufferLength, units=samples, default=0, type=int]
* Link Format - The format of the samples over the link.
[key=linkFormat, default=CS16, type=string, options=(CS16, CS12)]
* Skip Calibration - Skip automatic activation calibration.
[key=skipCal, default=false, type=bool]
* align phase - Attempt to align phase of Rx channels.
[key=alignPhase, default=false, type=bool]
Antennas: NONE, BAND1, BAND2
Corrections: DC offset, IQ balance
Full gain range: [-12, 64] dB
PAD gain range: [0, 52] dB
IAMP gain range: [-12, 12] dB
Full freq range: [0, 3800] MHz
RF freq range: [30, 3800] MHz
BB freq range: [2.5e-07, -2.5e-07] MHz
Tune args:
* LO Offset - Tune the LO with an offset and compensate with the baseband CORDIC.
[key=OFFSET, units=Hz, default=0.0, type=float]
* BB - Specify a specific value for this component or IGNORE to skip tuning it.
[key=BB, units=Hz, default=DEFAULT, type=float, options=(DEFAULT, IGNORE)]
Sample rates: [0.1, 61.44] MSps
Filter bandwidths: [5, 40], [50, 130] MHz
Sensors: lo_locked
* lo_locked (LO Locked): false
LO synthesizer is locked, good VCO selection.
Other Settings:
* TSP_CONST - Digital DC test signal level in LMS7002M TSP chain.
[key=TSP_CONST, default=16383, type=int, range=[0, 32767]]
* CALIBRATE - DC/IQ calibration bandwidth
[key=CALIBRATE, type=float, range=[2.5e+06, 1.2e+08]]
* ENABLE_GFIR_LPF - LPF bandwidth (must be set after sample rate)
[key=ENABLE_GFIR_LPF, type=float]
* TSG_NCO - Enable NCO test signal
[key=TSG_NCO, default=4, type=int, options=(-1, 4, 8)]

←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
←[1m←[31m[ERROR] TransferPacket: Write failed (ret=-1)←[0m
…

19

@Baer @ctlee

I had the “Write failed” error after trying to modify the FPGA code on a LimeSDR-mini. The only solution I found was to reprogram it using a USB blaster.

The first clone I bought didn’t work. The 2nd did work.

As Zack said before, I think it’s better to buy the official Blaster (https://www.digikey.com/en/products/detail/terasic-inc/P0302/2003484) if you have enough money.
You can try cheaper clone, but it’s not sure to work.

20

Hi Jay,
I actually didn’t modify any FPGA code on LimeSDR-mini, I bought the LimeSDR mini 2 year back, but recently only install the the driver and limesuite.

Is the card issues or driver ?