Work on a LimeSDR project with Google Summer of Code

Fantastic opportunity for students with digital design experience to get paid to work on an open source LimeSDR-based project over the course of the summer, courtesy of the Free and Open Source Silicon Foundation’s participation in Google Summer of Code 2017. For details see:

They look like two interesting projects. So the NIOS II is coupled to the Cyclone IV? But it’s an FPGA so isn’t it open? Or is it closed because it requires proprietary programming environment?

I have seen RISC-V offerings on crowdsupply recently.

Both projects sound like a re-plumbing of LimeSDR, one hardware and one software (toolchain). Is my understanding correct? With both having the intent and goal to make the LimeSDR even more open?

How would the RISC-V be coupled to the LimeSDR?

BTW love that article linked there on loading linux on a DE0-Nano! (have one of those kicking around here)

An FPGA is a programmable logic device, meaning that you write code using a Hardware Description Language (HDL), that describes how you want that logic configured. In the case of the LimeSDR we have, amongst other things, a NIOS II “soft core” processor. So what happens upon power-up is that a configuration file is loaded into the FPGA from flash and transforms it from a (mostly) blank canvas into a processor plus DSP and other stuff.

That NIOS II processor will then load a program and start executing it.

No, both involve reconfiguration of the FPGA — i.e. hardware. The one involving swapping out the NIOS II for a RISC-V soft core will also involve software, albeit porting the software — or more accurately, firmware — that previous ran on the former to now run on the latter. FuseSoC is software, but it’s role is more meta, in that it is used to package, integrate and build the IP cores that are written a HDL.

Thanks! Although just to note that this involved configuring the FPGA with an OpenRISC SoC design, before then booting Linux on this.

Now I get it. So the NIOS II soft core will be replaced by a RISC-V soft core. And RISC-V is open or the patent expired. Both?

FuseSoC is software, but it’s role is more meta, in that it is used to package, integrate and build the IP cores that are written a HDL.[/quote]

I would call this a new toolchain. Will Quartus still be required? When I used it with the DE0-Nano it felt like corporate bloatware. (apologies to the devs)

Well maybe down the road I dust off my DE0-Nano and figure out how to use it with my LimeSDR. I’m taking small steps right now.

It’s an open ISA, with reference implementations and toolchains etc. See: .

Yes, unless someone adds support for that device to Yosys.

PS. ORPSoC, as covered in that post you linked to, is the old name for FuseSoC.

That is good and will mean more eyes on it and more people using it.

Is that likely to happen?

Interesting because I find it a shame to see good projects wither.

The generally closed and proprietary nature of the FPGA tools does not help their adoption. But the ground swell that is open source is finding it’s way into corporate minds. Probably, and sadly really, mostly through attrition. i.e. out with the old and in with the new or perish

…just thought of this…
Is that something that could be proposed as a GSoC project?