Hello everyone,
I was wondering what is happening to the 12 bit databus (LMS_DIQ2_D[11…0]) after it goes into the “rx_path” module (inst35) on the FPGA, especially considering the change of the bus width from the 12 bit input vector to the 64 bit output vector (rx_pct_data[63…0]).
I’ve been experimenting with FPGAs for a while now and I tried to understand the mechanics of this module on my own but ooh wee, this is quite a bit for an amateur to chew on.
Since the data is coming in with I and Q seperated I assume the output vector rx_pct_data[63…0] of “rx_path” is in some form both parts together? Is there some form of documentation of what exactly this vector is made of?
E.g.
- 63…52 --> data_I
- 51…40 --> data_Q
- 39…XX --> other data
… or in some similar way?
I would really like to know if there is a signal that already includes I and Q part in one vector-signal?
I am very grateful for any kind of help!
Best regards,
Sulfur