About Myriad RF Tx Output

Projects Reference Development Kit
1

Hi,
I would like to transmit I/Q data by LMS6002D Tx part. However,
I feel confused the complex baseband mathematical equation is
a) Re{(I(t) + jQ(t))exp(j * 2 * pi * Fc * t)} or
b) Re{(I(t) + jQ(t))exp(-j * 2 * pi * Fc * t)}.
Thanks for your response.

2

Hello Dadvid,

In my equation (Labview) I’m using negative sign complex conjugation function. You can figure our on the bench, which works correctly. Generate one 1 MHz CW and see what do you see in the spectrum.

Andrew,

3

@andrewhux. You mentioned labview, so i think you can help me. I have labview and zipper/myriadrf interaced to a sbRIO board. I’ll be happy if you help me start. So Any idea or labview code example Would be very wellcome.
Thanks alot.

4

Hello Bachir,

You can download Labview vi from this [link]. This vi generates CW samples for I and Q paths, for desired frequency and DAC sampling frequency. Also, it has manual IQ imbalance correction algorithm.

Please note that samples are generated in unsigned value format ( LMS6 DAC required two’s compliment).

Best,
Rich

5

Thanks @RicardasVadoklis for your help.
But i see samples generated in signed 16bit integers. Correct me if i’m wrong.
My questions may be those of a begginer, but could you tell me how to get that code implemented in my target (sbRIO) in order to function as standalone system (sbRIO board interfaçed with zipper/myriadrf).

Thank you again,
Bachir

6

@Bachir the representation of the data array are in signed 16bit integer format, but data itself are generated as unsigned format (min data 0, max data 4096).

I’m not aware of the sbRIO, hence I don’t know how Labview driver is operating on the given platform. But first step is to connect sbRIO and Zipper boards together. Here you are looking to connect all DIQ , IQSEL and CLK lines. If you are looking to control SPI via sbRIO, connect them too. Make sure that IO level are matching rbRIO requirements. The IO levels are configurable on Zipper board (form 1.8 V to 3.3V).

The shared code is generating the samples for a given parameters. It has 5 input parameters:

  1. DAC frequency (MHz) - The DAC sampling frequency in MHz is 2 times lower the TxCLK.
  2. CW(MHz) - Desired CW frequency in MHz
  3. Back Off - Signal level scaling. Max scaling is 1.
  4. Gain Imbalance, dB - Corrects IQ Gain imbalance, value in dBs
  5. Phase error, - Corrects IQ phase error, value in Deg.

Output value are 3:

  1. Samples - the samples that are generated for the continuous waveform. The samples may vary with the input parameters.
  2. Sin data - In- phase component data
  3. Cos data - quadrature component data

To use this driver you need to have vi that would able to drive Zipper board.

I hope this helps.

Best,
Rich

7

@RicardasVadoklis, That helps a lot.
Well now i’m working on the hardware, connecting the lines. Then i will put this code in my target which contains Real time processor and FPGA in the same time. I will be bak.
Thank you,
Bachir

8

@RicardasVadoklis,
I’m now working on the receive side. Could you help me with this. Do you have some Labview vi for acquiring IQ signals.
I started doing this and i have a small question concerning data representation. Zipper board outputs 12 bits two’s complement data and i want to store this data in U16 integers. So what about the sign bit?
Thanks alot
Bachir

9

Hello Bachir,

Here is the example file used in Labview for getting 12 bit IQ data out of 16 bit data [link].

I uses exclusive or to convert Two’s complement to unsigned value.

Best,
Rich

10

Hi Rich,
Thank you for your help.
In the example vi, why do you delete the first 8 elements from the input data array?
Second question, i don’t understand the IQ select boolean.
Thanks again,
Bachir

11

Hello Bachir,

I’m just filtering first 8 data samples. I think this was done due to the DIO card that I was using. You can remove it.

To define IQ select polarity I need to read 13 th bit value. So I’m using very primitive filter do define it, and based on it outcome, I can filter data array to I and Q samples. When the first sample polarity defined, “I” for instance, I will know that the second will be Q.

I hope this helps,
Rich

12

Thank you Rich,
I don’t understand why 13 th bit in the input data is the IQ select polarity. IQ select is an external signal provided by Myriad board. So how did you build the input data integer array?

Your effort helps me a lot in kicking off my project.

Bachir

13

Bachir,

In my setup I’m using DIO card [link] connected to the Zipper + myriadRF board tandem. The DIO card is connected to J7 connector on Zipper board. I’m routing data to DIO card in such way that IQ sel pin is connected to 13th bit on DIO card.

I hope this helps.
Rich

14

Rich,
Connecting IQ sel pin to 13th bit was a good idea for me.
Thanks.
Bachir