Yes you are correct.
Just be carful do not mix term when we talk about DAC / ADC sampling data rate and sampling frequency

You mentioned:

Max. Sampling Frequency data rate = 80MHZ

max. clk frequency= 80mhz

In LMS6002D datasheet you will find terms such as “DACs sample rate” and “IQ interface data rate”

DACs sample rate is always twice lower then IQ interface data rate. In example: if DACs sample rate is max 40 Mhz, then IQ interface data rate max can be 80 MHz.

As you will find in the same datasheet sampling clock for DAC / ADC are TX_CLK / RX_CLK. In the LMS6002D for DACs/ADCs sampling they are divided by two, which means that DACs / ADCs sample rate is always twice lower then Clock frequency (TX_CLK / RX_CLK). So basically it means that max IQ interface data rate is always the same as max Clock frequency (TX_CLK / RX_CLK). So if these are the frequencies and rates you have had in mind, then yes, you are correct.