So, I would like to know how sample rates “work” in the LimeSDR. The master clock is at 30.72MHz, from the messages I get during start-up, but through Soapy/gr-osmosdr, I can
ask for sample-rates that aren’t integer fractions of the master-clock. I don’t get any error messages.
So, does something “underneath” change the master-clock rate? Is there a fractional resampler in the FPGA? Does it just not give error messages for “impossible” sample-rates?
Inquiring minds want to know, etc, etc.
30.72MHz is just a reference clock for PLLs inside of LMS7002M chip. PLLs inside of LMS7002M can generate desired (well, there is a range, of course) frequencies for you.
Thanks, Zack.
So another, related question is how is the filter+decimation “distributed” in the design–is it
all done in the LMS chip, or is there also the usual CIC decimator (or similar) in the FPGA?
Hi @mleech,
It is all done in LMS7002M. No additional filters in FPGA. Check digital path structures in Figure 11 & 12 in LMS7002M datasheet.
OK, so in the “factory” FPGA image, there’s isn’t much DSP going on in there, I gather…