Looks a bit wide + about 10db loss, compared to the 40M sampling.
Wondering what is the maximum clock frequency that LimeSDRMini can provide to LMS7? The base clock (40M?) can be tuned by the DAC, but how much is unclear.
To properly have the LMS7002M decimate using HBD_OVR_RXTSP, you must also reduce MCLK to prevent the FPGA from oversampling the output. You will need to modify register 0x002B to enable the divider (0x002B[0]=1) and then load the correct MCLK frequency in register 0x002C by updating RXTSPCLKA_DIV[7:0] appropriately.