Test using 40M sample rate, looks good:
Next, try to apply decimation for improved filtering, setting 2x decimation along with 80M sampling rate goes bad:
I would expect this to work because sampling rate out of LMS7 is still 40M.
@andrewback Is this something that could be fixed?
LimeSuite Build date: 2018-04-24
Gateware: 1.24
Gqrx setup: driver=lime,soapy=0
That looks to me like the decimation stage is saturating at some point. If you reduce the signal level, does it clean up?
Hi @gasparka,
Looks like bad settings. Could you save register ini file with LimeSuiteGUI and share it.
@N0YKG gain has no effect, there is some frequency dependency of the test tone
@Zack trying to read the registers with ‘Chip–>GUI’ has no effect, even though i am connected:
[14:51:03] INFO: Connected Control port: LimeSDR-Mini FW:5 HW:0 Protocol:1 GW:1.24 Ref Clk: 40.00 MHz
I tested the device with 80M sample rate and no decimation:
Wondering what is the maximum clock frequency that LimeSDRMini can provide to LMS7? The base clock (40M?) can be tuned by the DAC, but how much is unclear.
You have to push “Save” button after that.
What i meant is that presing Chip-GUI does not update the values in the GUI, i assumed saving the default values would not be that useful.
Anyhow i have now done it (Connect, Chip->GUI, Save):
@Zack I set the decimation in gqrx, then exit and use LimeSuite. Is it possible to set the decimation via Soapy interface?
I got it working with Soapy.
Here is the PR:
To properly have the LMS7002M decimate using HBD_OVR_RXTSP, you must also reduce MCLK to prevent the FPGA from oversampling the output. You will need to modify register 0x002B to enable the divider (0x002B[0]=1) and then load the correct MCLK frequency in register 0x002C by updating RXTSPCLKA_DIV[7:0] appropriately.
