I’ve run the LimeQuickTest on a 15sec loop immediately after boot, see log below. Seems to take just over a minute after boot to fail the test.
For what it’s worth, there seems to have been a change in the devices behavior from 19.01 - > 19.04. After upgrading firmware, the device can now calibrate SXR and SXT properly at all the frequencies I’ve tried so far. Could be attributed to commit 6feb479 where they changed the gain to meet tune.
Anyways, hope these logs help,
Stew
pi@raspberrypi:~ $ while sleep 15; do LimeQuickTest; done
[ TESTING STARTED ]
->Start time: Sat May 18 21:17:43 2019
[ Clock Network Test ]
->REF clock test
Test results: 21760; 40981; 60203 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5154065 (min); 5154089 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-11.9 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.2 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 3.35 seconds
[ TESTING STARTED ]
->Start time: Sat May 18 21:18:02 2019
[ Clock Network Test ]
->REF clock test
Test results: 20599; 39821; 59042 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5154068 (min); 5154091 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.3 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.5 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 3.32 seconds
[ TESTING STARTED ]
->Start time: Sat May 18 21:18:21 2019
[ Clock Network Test ]
->REF clock test
Test results: 11860; 31082; 50303 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5154070 (min); 5154094 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.5 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.6 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 3.31 seconds
[ TESTING STARTED ]
->Start time: Sat May 18 21:18:39 2019
[ Clock Network Test ]
->REF clock test
Test results: 1227; 20448; 39670 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5154072 (min); 5154096 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.6 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.7 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 3.32 seconds
[ TESTING STARTED ]
->Start time: Sat May 18 21:18:58 2019
[ Clock Network Test ]
->REF clock test
Test results: 63708; 17393; 36615 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5154073 (min); 5154097 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.7 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
SetFrequencySXT(752 MHz) - cannot deliver frequency
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 3.21 seconds