RF Loopback failure - LimeNET Micro

#1

HI all,

I just got my LimeNET Micro on Friday. I want to say congratulations to the development team, they put together a really nice board. I’ve run into a bit of an issue after running LimeQuickTest.

pi@raspberrypi:~ $ LimeQuickTest 
[ TESTING STARTED ]
->Start time: Sat May 18 21:40:59 2019


[ Clock Network Test ]
->REF clock test
  Test results: 31324; 50547; 4231 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154092 (min); 5154117 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-13.7 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
SetFrequencySXT(752 MHz) - cannot deliver frequency
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 3.20 seconds

The test environment is latest raspbian with latest LimeSuite with updated FPGA gateware. I’ve had 2 instances of this test passing (out of ~15 attempts), both successful self tests occured right after rebooting. Anyone at Myriad/Lime want to help me go through some troubleshooting steps?

EDIT:

I did a little more digging. I unplugged the LimeNET Micro for 10min and waited for the whole device to cool down. After powering on, I quickly ran the LimeQuick test and observed the loopback tests passing with a TX of -11.9 dBFS at 1800MHz and RX of -12.1 dBFS at 752MHz (not sure how those powers compare to those expected). Over the course of a minute I observed the powers degrade by another 0.6 dBFS to a final passing self test with values of -12.6dBFS on both TX and RX. Is the loopback all on chip? If so, could the 7002M be overheating?

Thanks,
Stew

#2

Hi @knGyCVGR,

Could you post a few logs when test fails.
Note please, that settings of test software are adopted for cold board, i.e. it is tuned for production testing. After 5 minutes, for instance, parameters may become different, but this is expected.

#3

Hi Zach,

I’m away from my device this week at a conference, I’ll post logs of the QuickTest when I get back. The results show a pretty linear decline in dBFS (Rx and Tx) over the course of a couple minutes after startup. The lowest level I saw was -13.6dBFS RX during a failed QuickTest.

I’ve seen improvements in the power levels by pointing a fan at the RF cans during operation. I may mount a couple of heat sinks to mitigate the issue.

Stew

#4

I’ve run the LimeQuickTest on a 15sec loop immediately after boot, see log below. Seems to take just over a minute after boot to fail the test.

For what it’s worth, there seems to have been a change in the devices behavior from 19.01 - > 19.04. After upgrading firmware, the device can now calibrate SXR and SXT properly at all the frequencies I’ve tried so far. Could be attributed to commit 6feb479 where they changed the gain to meet tune.

Anyways, hope these logs help,

Stew

pi@raspberrypi:~ $ while sleep 15; do     LimeQuickTest; done
[ TESTING STARTED ]
->Start time: Sat May 18 21:17:43 2019


[ Clock Network Test ]
->REF clock test
  Test results: 21760; 40981; 60203 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154065 (min); 5154089 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-11.9 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
  CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.2 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests PASSED <=

Elapsed time: 3.35 seconds

[ TESTING STARTED ]
->Start time: Sat May 18 21:18:02 2019


[ Clock Network Test ]
->REF clock test
  Test results: 20599; 39821; 59042 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154068 (min); 5154091 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.3 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
  CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.5 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests PASSED <=

Elapsed time: 3.32 seconds

[ TESTING STARTED ]
->Start time: Sat May 18 21:18:21 2019


[ Clock Network Test ]
->REF clock test
  Test results: 11860; 31082; 50303 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154070 (min); 5154094 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.5 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
  CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.6 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests PASSED <=

Elapsed time: 3.31 seconds

[ TESTING STARTED ]
->Start time: Sat May 18 21:18:39 2019


[ Clock Network Test ]
->REF clock test
  Test results: 1227; 20448; 39670 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154072 (min); 5154096 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.6 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
  CH0 (SXR=750.0MHz, SXT=752.0MHz): Result:(-12.7 dBFS, 2.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests PASSED <=

Elapsed time: 3.32 seconds

[ TESTING STARTED ]
->Start time: Sat May 18 21:18:58 2019


[ Clock Network Test ]
->REF clock test
  Test results: 63708; 17393; 36615 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5154073 (min); 5154097 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 03 08 13 03 08 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Testing using internal LMS7002M loopback
->Run Tests (TX_1-> LNA_H):
  CH0 (SXR=1800.0MHz, SXT=1802.0MHz): Result:(-12.7 dBFS, 2.00 MHz) - PASSED
->Run Tests (TX_2 -> LNA_L):
SetFrequencySXT(752 MHz) - cannot deliver frequency
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 3.21 seconds