Howdy,
I put the LimeSDR down for quite some time as I couldn’t get the desktop SW configured correctly and then ran out of time, but am back at it. I’m on a Mac and installed LimeSuite with brew which worked brilliantly, but . . .
I can’t update the FW on the LimeSDR using LimeUtil --update. I ran LimeQuickTest and got an OK, but the same FW mismatch that came up with LimeUtil. I’ve tried following the links that come up in the LimeUtil error, but they don’t resolve.
I then tried doing the update in a Windows VM using the Pothos SDR suite, but couldn’t get the drivers to recognize the board - sigh.
Eventually after stumbling on a post here I go to the firmware downloads dir on the MyriadRF site (http://downloads.myriadrf.org/project/limesuite/) but am uncertain which files to download for my board - can someone tell me which images for the FW and FPGA I should download. I’ve included the LimeQuickTest output below.
One note, I’ve never touched the FW on this board, so the config mismatch is factory.
Thanks -
Art
LimeQuicktest
[ TESTING STARTED ]
->Start time: Thu Mar 7 15:22:31 2019
Firmware version mismatch!
Expected firmware version 4, but found version 2
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update
Gateware version mismatch!
Expected gateware version 2, revision 18
But found version 2, revision 5
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update
->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009060B0046361C
Serial Number: 0009060B0046361C
[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 40365; 44121; 47877 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112949 (min); 5113085 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 10 0C 1D 10 0C 1D 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-14.1 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-16.3 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-15.3 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-17.0 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-17.7 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-14.7 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 1.43 seconds