Dear All,
We have a low bandwidth application where we need around 200 kSPS.
We also want to reduce the USB3 bandwidth as we are using an embedded PC.
We tried to reduce the sampling rate using the Osmocom Source/ Sink blocks in GNU Radio but we are getting errors below 1.5 MSPS. We would prefer 8MSPS decimate by 32 to get 250 kSPS.
Is there a way to set the HW decimate so that we can;
Reduce the USB3 bandwidth (more reliable)
Get rid of the decimator block in GNU Radio (lower CPU, better for embedded boards)
The ultimate solution would be an Interpolator inside the FPGA but for now we need a workaround.