Max RX sampling rate of LimeSDR-mini without USB transfer

Projects LimeSDR
1

Hello,
What is the max sampling rate that can be configured in the FPGA (MAX10) if we want only to read out the RX data from LMS7002M? (Without a further transfer of the data over USB)

2

160M. I am currently using 80M on LimeSDR-Mini and it works well.
My setup is to sample with 160M and in the LMS decimate by 2, thus giving 80M filtered bandwidth in the FPGA.

You need custom cooling if you try this on the mini.

3

Thanks for the helpful answer.
Do you know, where can I find information about how to cool the LimeSDR-Mini?
In your setup with 80M: Does the MAX10 still have some capacity to be used for further signal processing?

4

I will post something about the cooling tomorrow.
MAX10 is basically full on LUTs and BRAM, multipliers are free.

For my use-case i deleted most of the stuff in MAX10 and replaced with DSP code.
Things that i know i regressed:

  • Everything about TX
  • Timed-samples/packages (receiving unpackaged samples requires hack in LimeSuite)
  • PLL tuning - i have a constant sampling delay, which only works for 40M or 80M sample rate (and possibly inbetween)

Things that i kept:

  • Interface to send back samples, with reduced samplerate
  • All related to MCU, so LMS control fully works
  • FPGA programming interface

After that you have like almost all the BRAM and 80% LUTS.I could share this if you find it useful,
but be warned, hacking around in the FPGA sources is time consuming + potential mental health issues.

5

Thank you for the detailed answer.
It would be very helpful for me if you could share your config and FPGA sources

6

Can you publish the utilization report. I wonder if my PSK demodulator code would fit into it.

7

Sorry i am too busy atm, will push some info here next week!

8

Here is the synthesis report:

Quartus Prime Version	18.0.0 Build 614 04/24/2018 SJ Lite Edition
Revision Name	LimeSDR-Mini_lms7_trx
Top-level Entity Name	lms7_trx_top
Family	MAX 10
Device	10M16SAU169C8G
Timing Models	Final
Total logic elements	4,238 / 15,840 ( 27 % )
Total registers	2566
Total pins	113 / 130 ( 87 % )
Total virtual pins	0
Total memory bits	92,160 / 562,176 ( 16 % )
Embedded Multiplier 9-bit elements	0 / 90 ( 0 % )
Total PLLs	1 / 1 ( 100 % )
UFM blocks	1 / 1 ( 100 % )
ADC blocks	0 / 1 ( 0 % )