LimeSDR USB fails test every other time

N0YKG · 31 March 2020 01:24

My LimeSDR USB fails every other time I access it. For example, I can run a GRC flowgraph once, but stopping and starting gives me a zero gateware version.

LimeQuickTest
[ TESTING STARTED ]
->Start time: Mon Mar 30 20:22:08 2020

Read(64 bytes) failed
Gateware version mismatch!
Expected gateware version 2, revision 17
But found version 0, revision 0
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009060A02432F23
Serial Number: 0009060A02432F23

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 1; 0; 0 - PASSED
->Si5351C test
CLK0: 2 / 17554 - FAILED
CLK1: 2 / 17554 - FAILED
CLK2: 2 / 17554 - FAILED
CLK3: 2 / 17554 - FAILED
CLK4: 2 / 17554 - FAILED
CLK5: 2 / 17554 - FAILED
CLK6: 2 / 17554 - FAILED
FAILED
->VCTCXO test
Results : 4 (min); 4 (max) - FAILED
FAILED
->ADF4002 Test
Error
FAILED
->Clock Network Test FAILED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 02 15 11 02 15 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTest() failed
->LMS7002M Test FAILED

[ RF Loopback Test ]
->Configure LMS
SetFrequencySXT(1250 MHz) - cannot deliver frequency
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 0.99 seconds

Immediately rerunning the test:

LimeQuickTest
[ TESTING STARTED ]
->Start time: Mon Mar 30 20:22:25 2020

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009060A02432F23
Serial Number: 0009060A02432F23

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 18369; 22125; 25881 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->VCTCXO test
Results : 5112916 (min); 5113046 (max) - PASSED
->ADF4002 Test
Result: 10 - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 02 15 11 02 15 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-14.6 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-16.5 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-20.2 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-30.7 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-16.7 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-13.9 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 1.39 seconds

Lather, rinse, repeat.

This is on a USB3 connection, with both the USB connectors plugged in, so the board should have plenty of power. I also have a fan on the board, so that it won’t overheat, and it seems to be reasonably warm, not hot.

Dominik · 31 March 2020 08:09

Expected gateware version 2, revision 17
But found version 0, revision 0
Follow the FW and FPGA upgrade instructions:
Lime Suite - Myriad-RF Wiki
Or run update on the command line: LimeUtil --update

Did you try to update your device by execution of LimeUtil --update yet?

This will flash your device matching the version installed on your system. But be careful if it shows Firmware and Gateware update is not required. I had once a similar problem and it turned out for me that the actually FPGA raw binary file download by the LimeUtil was corrupt (partial download). If this happened to you by incident as well, you could delete the cached firmware files to trigger a new download. These are stored to the App data directory and can be determined by LimeUtil --info. You can find all downloads in the folder images then.

Alternatively, you could manually download the gateway version 2 revision 17 images for your device, e.g. FPGA Gateware r2.17 and Image 1.4 r4.0 from LimeSuite 18.06 (Sep 2018).

More information on this is available on LimeSDR_Firmware_Management. It might help already.

Read(64 bytes) failed

It might also help to push once the SW1 FX3 reset push-button. You find it next to the USB connector above the first IC13 on the top board.

N0YKG · 31 March 2020 11:28

Thanks for the input, but:

as you will note, the board works every other time - as in, without reflashing, it recovers and will operate every second time I run the test.
additional information: this behavior only shows up on USB3 - on USB2 it will run the test consistently. There appears to be a problem with the interface at USB3 speeds only.

Dominik · 1 April 2020 16:13

Do you know which firmware and FPGA gateway is flashed to your device? I have a similar USB 3.0 issue not getting it to stream data properly and USB 2 is at least partially functional for me as well.

Read(64 bytes) failed
Gateware version mismatch!
Expected gateware version 2, revision 17
But found version 0, revision 0

But I don’t get this type of error message.

N0YKG · 1 April 2020 18:05

Right now I have 2.19.

Dominik · 4 April 2020 12:57

Maybe check if this is applicable https://discourse.myriadrf.org/t/limesdr-hardware-problem-usb-controller/4637 or otherwise https://discourse.myriadrf.org/t/limesdr-usb-gateware-version-is-not-recognizeable-temperature-related/3439/12.

At least for me it looks similar due to the Read(64 bytes) failed message. @andrewback

N0YKG · 6 April 2020 01:45

Firmware 4.0, gateware 2.22 seems to do better.

TehWan · 6 April 2020 12:04

Are you on Linux? If so, is your USB3 controller made by AMD? If so, it’s a known bug with the Linux kernel.

N0YKG · 7 April 2020 01:37

Yes, it’s an AMD Matisse board for a Threadripper CPU. Thanks for the pointer!