[ TESTING STARTED ]
->Start time: Tue Dec 3 07:36:32 2019
->Device: LimeSDR Mini, media=USB 3, module=FT601, serial=1D40F74B21DAD0, index=0
Serial Number: 1D40F74B21DAD0
[ Clock Network Test ]
->REF clock test
Test results: 3705; 16902; 30099 - PASSED
->VCTCXO test
Results : 6710989 (min); 6711151 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 06 1D 12 06 1D 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-25.6 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-12.4 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 3.65 seconds
[ TESTING STARTED ]
->Start time: Tue Dec 3 07:37:18 2019
->Device: LimeSDR Mini, media=USB 3, module=FT601, serial=1D40F74B21DAD0, index=0
Serial Number: 1D40F74B21DAD0
[ Clock Network Test ]
->REF clock test
Test results: 10160; 23357; 36554 - PASSED
->VCTCXO test
Results : 6711004 (min); 6711167 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 06 1D 12 06 1D 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-15.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-12.1 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 3.62 seconds