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[13:43:41] INFO: Reference clock 30.72 MHz
[13:43:41] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.23 Ref Clk: 30.72 MHz
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: LML RX phase search FAIL
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:44:46] ERROR: LML TX phase search FAIL
[13:45:05] ERROR: TuneVCO(CGEN) - failed to lock (cmphl!=0)
[13:45:05] ERROR: SetFrequencyCGEN(80 MHz) failed
[13:45:21] INFO: Reference clock 30.72 MHz
[13:45:21] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.23 Ref Clk: 30.72 MHz
[13:45:30] ERROR: MCU FIFO full
[13:45:30] ERROR: MCU FIFO full
[13:45:30] ERROR: MCU FIFO full
[13:45:30] ERROR: MCU FIFO full
[13:45:30] ERROR: MCU FIFO full
[13:46:39] ERROR: TuneVCO(CGEN) - failed to lock (cmphl!=0)
[13:46:39] ERROR: SetFrequencyCGEN(61.44 MHz) failed
[13:46:39] ERROR: MCU FIFO full
[13:46:39] ERROR: Tune Tx Filter: failed to program MCU
[13:46:46] ERROR: MCU FIFO full
[13:46:46] ERROR: Tune Rx Filter: failed to program MCU
[13:48:26] DEBUG: M=160, N=2, Fvco=605.365 MHz
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] ERROR: LML RX phase search FAIL
[13:49:32] DEBUG: M=240, N=12, Fvco=1296.000 MHz
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[13:49:32] ERROR: SetPllFrequency: timeout, busy bit is still 1
[13:49:32] ERROR: LML TX phase search FAIL
[13:49:32] DEBUG: M=255, N=51, Fvco=1296.000 MHz
[ TESTING STARTED ]
->Start time: Mon Jan 11 13:54:59 2021
->LimeSuite version: 20.10.0-g1480bfea
->Device: LimeSDR-USB, media=USB 2.0, module=FX3, serial=00090726074F183B, index=0, HW=4, GW=2.23
Warning: USB3 not available
Serial Number: 00090726074F183B
Temperature internal ADC calibration failed
Chip temperature: 0 C
[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 44964; 48720; 52476 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112959 (min); 5113087 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 08 01 12 08 01 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTest() failed
->LMS7002M Test FAILED
[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(61.44 MHz) failed
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 5.07 seconds
Damn. all right i threw $300
I dropped limesdr
Sorry, you mean you physically dropped the board?
Yes. I dropped limesSDR
1 Like
OK, this looks to be a 0 ohm jumper:
https://www.digikey.co.uk/products/en?keywords=311-0.0JRTR-ND
You can look up the parts in the BOM spreadsheets:
1 Like
Worked limesdr
THAMK YOU !!!
2 Likes