ERROR: SetPllFrequency: error configuring phase

ogun · 30 March 2018 13:30

Hello everyone,

Recently I am getting this error from the gnuradio. every driver and gnuradio was installed from the source. Any ideas?

Best

andrewback · 2 April 2018 09:25

@IGnasJ can you advise, please.

sglee · 2 April 2018 12:17

I am getting same error too

Zack · 3 April 2018 13:01

We are checking it.

mleech · 3 April 2018 19:13

Just to add a “me too”.

Built from latest GIT and latest Firmware/Gateware.

I’m running two channels, at 5.0Msps.

ogun · 5 April 2018 14:24

It might be about gateware version 15 when I downgraded to 12 It was fine and just getting warning: upgrade the gateware version to 15

btashton · 14 April 2018 06:34

@Zack Any update on this? I am seeing it as well.

EDIT:
I see this is version 16 as well when i try and load self_test.ini

Zack · 16 April 2018 06:44

Hi,

It is fixed in the latest gateware (ver. 2.16).

btashton · 16 April 2018 06:55

@zack that is the version I was using.

Zack · 16 April 2018 07:31

Hi @btashton,

Update the LimeSuite too.

btashton · 16 April 2018 18:23

This is the commit that I built off of.
Maybe there is a hardware issue with my LimeSDR that this is bringing to light? https://github.com/myriadrf/LimeSuite/commit/67dcef198dc8ec79116085595bb34938b182dfdd

btashton · 17 April 2018 03:09

@Zack I’m starting to think there is a hardware issue here and this new firmware is just highlighting the clock issue.
Attached is the test signal from the quick test. It looks off by about 200MHz. Any thoughts?

Looking at the REF CLK out, there is a small signal at the expected 30.72MHz, but a much larger signal at 27MHz

Zack · 17 April 2018 08:04

Hi @btashton,

Could you share more information about your setup, please. I assume this is LimeSDR-USB board and you run LimeSuiteGUI and self_test.ini configuration file (it looks like you don’t, while TX frequency in this file is set to 2.1GHz). Do you follow Quick Test procedure step by step? Do you change SXT frequency? Do you push “Calculate” button in SXT tab?

First of all, you have to solder R151 if you want to get REF_CLK_OUT signal out, while this resistor is no fit by default. This is an excerpt from schematic:

This is where R151 is located on PCB:

27MHz is used as a reference clock for SDRAMs hence you pick up it too.

btashton · 18 April 2018 00:49

Running LimeSuite that I just built from master I loaded the latest firmware:

programming: completed (/home/bashton/.local/share/LimeSuite/images/18.04/LimeSDR-USB_HW_1.4_r2.16.rbf)

With this firmware I cannot load the setf_test.ini file it show this and then a dialog saying failed to open the file.

[17:37:22] DEBUG: Estimated reference clock 30.6586 MHz
[17:37:22] INFO: Reference clock 30.72 MHz
[17:37:22] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.16 Ref Clk: 30.72 MHz
[17:37:28] DEBUG: INT 63, FRAC 0, DIV_OUTCH_CGEN 3
[17:37:28] DEBUG: VCO 1966.08 MHz, RefClk 30.72 MHz
[17:37:28] DEBUG: csw 57; interval [54, 60]
[17:37:28] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[17:37:28] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[17:37:28] ERROR: SetPllFrequency: error configuring phase
[17:37:28] DEBUG: M=252, N=12, Fvco=1290.240 MHz

The image I took above was using the gateware 2.12, but I had been playing with Part 5 of this https://wiki.myriadrf.org/LimeSDR-USB_Quick_Test which sets it to 800MHz

Here are the logs when I try to run the first section of the Quick test:
[17:43:22] WARNING: Gateware version mismatch!
Expected gateware version 2, revision 16
But found version 2, revision 12
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update

[17:43:22] DEBUG: Estimated reference clock 30.6586 MHz
[17:43:22] INFO: Reference clock 30.72 MHz
[17:43:22] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.12 Ref Clk: 30.72 MHz
[17:43:29] DEBUG: INT 63, FRAC 0, DIV_OUTCH_CGEN 3
[17:43:29] DEBUG: VCO 1966.08 MHz, RefClk 30.72 MHz
[17:43:29] DEBUG: csw 59; interval [56, 62]
[17:43:29] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[17:43:29] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[17:43:46] DEBUG: INT 132, FRAC 753664, DIV_LOCH 0, EN_DIV2_DIVPROG 0
[17:43:46] DEBUG: VCO 4200.00 MHz, RefClk 30.72 MHz
[17:43:46] DEBUG: ICT_VCO: 255
[17:43:46] DEBUG: csw=64	cmphl=0
[17:43:46] DEBUG: csw=96	cmphl=0
[17:43:46] DEBUG: csw=112	cmphl=3
[17:43:46] DEBUG: csw=104	cmphl=3
[17:43:46] DEBUG: csw=100	cmphl=2
[17:43:46] DEBUG: csw=102	cmphl=2
[17:43:46] DEBUG: csw=103	cmphl=3
[17:43:46] DEBUG: Failed to lock
[17:43:46] DEBUG: csw=192	cmphl=3
[17:43:46] DEBUG: csw=160	cmphl=3
[17:43:46] DEBUG: csw=144	cmphl=3
[17:43:46] DEBUG: csw=136	cmphl=3
[17:43:46] DEBUG: csw=132	cmphl=3
[17:43:46] DEBUG: csw=130	cmphl=3
[17:43:46] DEBUG: csw=129	cmphl=3
[17:43:46] DEBUG: Failed to lock
[17:43:46] DEBUG: cmphl=2
[17:43:46] DEBUG: VCOL : csw=99 tune ok
[17:43:46] DEBUG: ICT_VCO: 255
[17:43:46] DEBUG: TuneVCO(SXT) - VCO too high
[17:43:46] DEBUG: VCOM : csw=0 tune fail
[17:43:46] DEBUG: ICT_VCO: 255
[17:43:46] DEBUG: TuneVCO(SXT) - VCO too high
[17:43:46] DEBUG: VCOH : csw=0 tune fail
[17:43:46] DEBUG: Selected: VCOL
[17:43:46] INFO: SXT frequency set to 2100.000000 MHz
[17:43:53] DEBUG: ICT_VCO: 255
[17:43:53] DEBUG: csw=64	cmphl=0
[17:43:53] DEBUG: csw=96	cmphl=0
[17:43:53] DEBUG: csw=112	cmphl=3
[17:43:53] DEBUG: csw=104	cmphl=3
[17:43:53] DEBUG: csw=100	cmphl=2
[17:43:53] DEBUG: csw=102	cmphl=2
[17:43:53] DEBUG: csw=103	cmphl=3
[17:43:53] DEBUG: Failed to lock
[17:43:53] DEBUG: csw=192	cmphl=3
[17:43:53] DEBUG: csw=160	cmphl=3
[17:43:53] DEBUG: csw=144	cmphl=3
[17:43:53] DEBUG: csw=136	cmphl=3
[17:43:53] DEBUG: csw=132	cmphl=3
[17:43:53] DEBUG: csw=130	cmphl=3
[17:43:53] DEBUG: csw=129	cmphl=3
[17:43:53] DEBUG: Failed to lock
[17:43:53] DEBUG: cmphl=2
[17:44:05] DEBUG: INT 63, FRAC 0, DIV_OUTCH_CGEN 3
[17:44:05] DEBUG: VCO 1966.08 MHz, RefClk 30.72 MHz
[17:44:05] DEBUG: csw 59; interval [56, 62]
[17:44:05] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[17:44:05] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[17:44:05] INFO: CGEN frequency set to 245.760000 MHz
[17:44:06] DEBUG: csw 59; interval [56, 62]
[17:44:06] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[17:44:06] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[17:44:49] DEBUG: INT 113, FRAC 196608, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7200.00 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXR) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXR) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=2
[17:44:49] DEBUG: csw=176	cmphl=3
[17:44:49] DEBUG: csw=168	cmphl=2
[17:44:49] DEBUG: csw=172	cmphl=2
[17:44:49] DEBUG: csw=174	cmphl=2
[17:44:49] DEBUG: csw=175	cmphl=2
[17:44:49] DEBUG: CSW: lowest=160, highest=175, selected=167
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=167 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 458752, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7215.36 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=3
[17:44:49] DEBUG: csw=178	cmphl=2
[17:44:49] DEBUG: csw=179	cmphl=3
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=170 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 720896, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7230.72 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=2
[17:44:49] DEBUG: csw=182	cmphl=3
[17:44:49] DEBUG: csw=181	cmphl=2
[17:44:49] DEBUG: CSW: lowest=166, highest=181, selected=173
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=173 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 458752, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7215.36 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=3
[17:44:49] DEBUG: csw=178	cmphl=2
[17:44:49] DEBUG: csw=179	cmphl=3
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=170 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 720896, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7230.72 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=2
[17:44:49] DEBUG: csw=182	cmphl=3
[17:44:49] DEBUG: csw=181	cmphl=2
[17:44:49] DEBUG: CSW: lowest=166, highest=181, selected=173
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=173 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 458752, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7215.36 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=3
[17:44:49] DEBUG: csw=178	cmphl=2
[17:44:49] DEBUG: csw=179	cmphl=3
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=170 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 720896, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7230.72 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=2
[17:44:49] DEBUG: csw=182	cmphl=3
[17:44:49] DEBUG: csw=181	cmphl=2
[17:44:49] DEBUG: CSW: lowest=166, highest=181, selected=173
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=173 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 458752, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7215.36 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=3
[17:44:49] DEBUG: csw=178	cmphl=2
[17:44:49] DEBUG: csw=179	cmphl=3
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=170 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 113, FRAC 720896, DIV_LOCH 3, EN_DIV2_DIVPROG 1
[17:44:49] DEBUG: VCO 7230.72 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOL : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too low
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=0
[17:44:49] DEBUG: csw=120	cmphl=0
[17:44:49] DEBUG: csw=124	cmphl=0
[17:44:49] DEBUG: csw=126	cmphl=0
[17:44:49] DEBUG: csw=127	cmphl=0
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=0
[17:44:49] DEBUG: csw=176	cmphl=2
[17:44:49] DEBUG: csw=184	cmphl=3
[17:44:49] DEBUG: csw=180	cmphl=2
[17:44:49] DEBUG: csw=182	cmphl=3
[17:44:49] DEBUG: csw=181	cmphl=2
[17:44:49] DEBUG: CSW: lowest=166, highest=181, selected=173
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOH : csw=173 tune ok
[17:44:49] DEBUG: Selected: VCOH
[17:44:49] DEBUG: INT 132, FRAC 819200, DIV_LOCH 0, EN_DIV2_DIVPROG 0
[17:44:49] DEBUG: VCO 4201.92 MHz, RefClk 30.72 MHz
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: csw=64	cmphl=0
[17:44:49] DEBUG: csw=96	cmphl=0
[17:44:49] DEBUG: csw=112	cmphl=3
[17:44:49] DEBUG: csw=104	cmphl=3
[17:44:49] DEBUG: csw=100	cmphl=2
[17:44:49] DEBUG: csw=102	cmphl=2
[17:44:49] DEBUG: csw=103	cmphl=2
[17:44:49] DEBUG: CSW: lowest=97, highest=103, selected=100
[17:44:49] DEBUG: csw=192	cmphl=3
[17:44:49] DEBUG: csw=160	cmphl=3
[17:44:49] DEBUG: csw=144	cmphl=3
[17:44:49] DEBUG: csw=136	cmphl=3
[17:44:49] DEBUG: csw=132	cmphl=3
[17:44:49] DEBUG: csw=130	cmphl=3
[17:44:49] DEBUG: csw=129	cmphl=3
[17:44:49] DEBUG: Failed to lock
[17:44:49] DEBUG: cmphl=2
[17:44:49] DEBUG: VCOL : csw=100 tune ok
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too high
[17:44:49] DEBUG: VCOM : csw=0 tune fail
[17:44:49] DEBUG: ICT_VCO: 255
[17:44:49] DEBUG: TuneVCO(SXT) - VCO too high
[17:44:49] DEBUG: VCOH : csw=0 tune fail
[17:44:49] DEBUG: Selected: VCOL

And the FFT which looks very noisy to me.

Zack · 19 April 2018 06:38

Hi @btashton,

Try to execute LimeSuiteGUI with admin rights.

btashton · 19 April 2018 13:23

@Zack
I ran this under Linux. It has no permission issue loading the file. The file loads fine when I have the old gateware on the board.

Zack · 19 April 2018 14:14

Hi @btashton,

Could you try this, please:

Use gateware version 2.16 with the latest LimeSuiteGUI;
Try to load self_test.ini file;
If it complains about permission issue, press OK;
Go to CGEN tab;
Push Calculate button and post the result here;
Change frequency to 80MHz;
Push Calculate button and post the result here.

btashton · 19 April 2018 21:39

@Zack It is not a permissions issue. It clearly loads the file, but fails to configure the hardware.

I just pulled the latest code from master and ran though the test anyway and both clock calculations failed:

[14:26:08] INFO: Disconnected control port
[14:26:20] INFO: Reference clock 30.72 MHz
[14:26:20] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.16 Ref Clk: 30.72 MHz
[14:26:30] DEBUG: INT 63, FRAC 0, DIV_OUTCH_CGEN 3
[14:26:30] DEBUG: VCO 1966.08 MHz, RefClk 30.72 MHz
[14:26:30] DEBUG: csw 57; interval [54, 60]
[14:26:30] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[14:26:30] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[14:26:30] ERROR: SetPllFrequency: error configuring phase
[14:26:30] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[14:27:54] DEBUG: INT 63, FRAC 0, DIV_OUTCH_CGEN 3
[14:27:54] DEBUG: VCO 1966.08 MHz, RefClk 30.72 MHz
[14:27:54] DEBUG: csw 58; interval [55, 61]
[14:27:54] DEBUG: M=252, N=6, Fvco=1290.240 MHz
[14:27:54] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[14:27:54] ERROR: SetPllFrequency: error configuring phase
[14:27:54] DEBUG: M=252, N=12, Fvco=1290.240 MHz
[14:27:57] INFO: CGEN frequency set to 245.760000 MHz
[14:28:13] DEBUG: INT 77, FRAC 131072, DIV_OUTCH_CGEN 14
[14:28:13] DEBUG: VCO 2400.00 MHz, RefClk 30.72 MHz
[14:28:13] DEBUG: csw 172; interval [170, 175]
[14:28:13] DEBUG: M=130, N=1, Fvco=1300.000 MHz
[14:28:13] DEBUG: M=195, N=3, Fvco=1300.000 MHz
[14:28:13] ERROR: SetPllFrequency: error configuring phase
[14:28:13] DEBUG: M=195, N=3, Fvco=1300.000 MHz
[14:28:15] INFO: CGEN frequency set to 80.000000 MHz

Zack · 20 April 2018 06:32

Hi @btashton,

Agree.

And one more request - could you describe status of LEDs, please.

btashton · 21 April 2018 01:22

@Zack I also just tried installing the power header to power the board via an external power supply and I got the same results. The LEDs are as follows:

PWR - Solid Green
FX3 - Solid Green or Red momentarily
FPGA1 - Blinking Green
FPGA2 - Blank

This seems to be the normal status.