Hi @Zack,
Here’s some results (Please don’t care about the USB2.0 notification, this is only due to the testing case).
[ TESTING STARTED ]
->Start time: Thu Dec 5 06:29:03 2019
->Device: LimeSDR Mini, media=USB 2.0, module=FT601, addr=24607:1027, serial=1D4C2C87C3DF04
Warning: USB3 not available
Serial Number: 1D4C2C87C3DF04
[ Clock Network Test ]
->REF clock test
Test results: 46018; 59214; 6875 - PASSED
->VCTCXO test
Results : 6711072 (min); 6711237 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 0C 13 02 0C 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-13.9 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-12.8 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.63 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:30:44 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D4C3888519F42
Serial Number: 1D4C3888519F42
[ Clock Network Test ]
->REF clock test
Test results: 60013; 7674; 20871 - PASSED
->VCTCXO test
Results : 6711037 (min); 6711192 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 0D 13 02 0D 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-13.6 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-13.5 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.41 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:49:37 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D4C2AFA909C94
Serial Number: 1D4C2AFA909C94
[ Clock Network Test ]
->REF clock test
Test results: 46468; 59665; 7326 - PASSED
->VCTCXO test
Results : 6711039 (min); 6711191 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 0C 13 02 0C 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-15.0 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-15.5 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.59 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:50:11 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D4249B13B7CB1
Serial Number: 1D4249B13B7CB1
[ Clock Network Test ]
->REF clock test
Test results: 61373; 9034; 22236 - PASSED
->VCTCXO test
Results : 6710994 (min); 6711160 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 07 1A 12 07 1A 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-12.9 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-12.3 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.47 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:50:32 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D4C2B8F2E8121
Serial Number: 1D4C2B8F2E8121
[ Clock Network Test ]
->REF clock test
Test results: 6578; 19769; 32973 - PASSED
->VCTCXO test
Results : 6710995 (min); 6711149 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 0C 13 02 0C 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-14.2 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-14.0 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.52 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:51:06 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D4C2A74EBC9F9
Serial Number: 1D4C2A74EBC9F9
[ Clock Network Test ]
->REF clock test
Test results: 37406; 50603; 63800 - PASSED
->VCTCXO test
Results : 6710988 (min); 6711144 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 0C 13 02 0C 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-13.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-13.2 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.43 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:51:59 2019
->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D42575299304B
Serial Number: 1D42575299304B
[ Clock Network Test ]
->REF clock test
Test results: 59289; 6950; 20147 - PASSED
->VCTCXO test
Results : 6711066 (min); 6711219 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 07 1B 12 07 1B 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-12.2 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-12.9 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED
=> Board tests PASSED <=
Elapsed time: 2.48 seconds
[ TESTING STARTED ]
->Start time: Thu Dec 5 15:52:54 2019
Board not supported
Failed to connect
I’m trying to collect more logs, but as some board are abroad, its harder.
Hope that you can help us.