Why not receiver PLL of lms6002D locked?

I design a new board :fpga+ LMS6002D, use fpga to configure the lms6002D. but now I encounter a big problem that the receiver PLL of LMS6002D can not locked.
The receiver PLL clk is 32.736 MHz, the desired frequency is 1575.42MHz, rx LPF is 1.25M.
the input frequcency is 1574.42MHz, but the IF frequency is not the desired 1MHz, see figure below. I am sure the SPI configure sequence is right.
my pcb layout of the loop filter is different with the evb6002(demo board). does it the matter? Do I need to change the loop filter.

Hi Wqiao,

I am currently in process of designing my board too.
Do you mind sharing what clock generator you used for PLL, and how is the schematic?

Thank you.