Lime6002 TXPLL doesn't lock

Hi! I’m trying to get an output frequency of 394.65MHz, at a reference frequency of 30.72MHz.external LF BW = 100kHz, register setting:
0X821F
0X8308
0X853A
0X860D
0X8700
0X8800
0X8981
0X8A00
0X8B08
0X9066
0X91C6
0X9200
0X9300
0X9488
0X95DD
0X968C
0X97E3
0X9840
0X99A1
0X9A03
0X9B76
0X9C38
0XA03F
0XA17A
0XA200
0XA300
0XA488
0XA591
0XA68C
0XA7E3
0XA840
0XA98B
0XAA03
0XAB76
0XAC38
0XB21F
0XB308
0XB402
0XB50C
0XB630
0XC002
0XC114
0XC280
0XC380
0XC40B
0XC550
0XC600
0XC740
0XC80C
0XC90C
0XCA18
0XCB50
0XCC00
0XCD00
0XD21F
0XD308
0XD402
0XD50C
0XD630
0XD794
0XD800
0XD909
0XDA20
0XDB00
0XDC00
0XDD00
0XDE00
0XDF1F
0XE21F
0XE308
0XE436
0XE501
0XE600
0XE700
0XE801
0XF001
0XF180
0XF280
0XF300
0XF400
0XF5D0
0XF678
0XF700
0XF81C
0XF937
0XFA77
0XFB77
0XFC18
0XFD00
Vtune = 1.2V, but fout = 393.6 . I change VCOCAP in all range, but the transmitter frequency is not the same as the programmed value
I tried to set the output frequency to 1578.6MHz (394,65*4), the settings of the registers remained the same, Fvco = 6.3144GHz , changed 0х15 = 0xd5 (Fvco/4) and 0x19 = B2 (VCOCAP= 50). Register setting
0X821F
0X8308
0X853A
0X860D
0X8700
0X8800
0X8981
0X8A00
0X8B08
0X9066
0X91C6
0X9200
0X9300
0X9488
0X95D5
0X968C
0X97E3
0X9840
0X99B2
0X9A03
0X9B76
0X9C38
0XA03F
0XA17A
0XA200
0XA300
0XA488
0XA591
0XA68C
0XA7E3
0XA840
0XA98B
0XAA03
0XAB76
0XAC38
0XB21F
0XB308
0XB402
0XB50C
0XB630
0XC002
0XC114
0XC280
0XC380
0XC40B
0XC550
0XC600
0XC740
0XC80C
0XC90C
0XCA18
0XCB50
0XCC00
0XCD00
0XD21F
0XD308
0XD402
0XD50C
0XD630
0XD794
0XD800
0XD909
0XDA20
0XDB00
0XDC00
0XDD00
0XDE00
0XDF1F
0XE21F
0XE308
0XE436
0XE501
0XE600
0XE700
0XE801
0XF001
0XF180
0XF280
0XF300
0XF400
0XF5D0
0XF678
0XF700
0XF81C
0XF937
0XFA77
0XFB77
0XFC18
0XFD00
my transmitter frequency is now the same as the programmed value.I change reg0x15 = 0xdd (Fvco/16), the transmitter frequency does not match the programmed value again (Fout =393.6 ). Change VCOCAP does not help.
How is this possible? Figure 3.4: PLL control in Programming-and-Calibration-Guide shows PLL feedback before division Fvco. Why does not the output frequency correspond to the programmed value when setting the VCO for the same frequency when the divider is changed (FREQSEL)?