We are ready to pay for this project

[booth]

Dear All,
We are ready to pay for the job described here:(Zynq board preferred)

LIMESDR-FPGA USB connection

Dear All, We have several DSP IP’s prepared for Xilinx FPGA. We want to test them with LIMESDR or LIMESDR mini. We plan to connect the LIMESDR or LIMESDR mini into the USB Host of an FPGA board. What we could not figure out is how to get the Stream for the USB and convert it to 10 bit I&Q + CLK which our DSP IP’s need to process the data. Has anyone tried this before? We guess that we can install GNU RADIO inside a ZYNQ FPGA’s ARM processor and get the data but sending it to the FPGA and co…

Please send a message if you interested.

[gwong]

If you have the funds, you may simply want to get a LMS7002 EVB v3 and a Digilent Zedboard. @joshblum has mentioned pulling this combo off in the past.

[zener]

If all you need is the I&Q you could simply capture the I&Q from the LimeSDR and store it in a file. Most Zynq boards have SD cards for boot. You could make a partition and put your file there (or raw data in the partition if that’s easier) and write a program to stream it over the AXI bus into your FPGA.

If you need real time live I&Q you could switch the source from the SD card to USB. This is a bit more complex, but then you have at least developed and debugged the AXI streaming interface into the FPGA fabric.

Or if you want to test your Lime interface as well you could get the Lime FMC development kit as suggested by somebody else. Or you can try to get hold of a XTRX board which has a Xilinx Artix 7 connected to the Lime. Early bird/beta tester board owners might be willing to sell one.

[booth]

That is exactly what we want and ready to pay! “Getting the USB Stream into FPGA and converting it to IQ and CLK for demodulation”
Thanks for the advice on the AXI bus but we prefer a solution.