Transmitter Output Level

We are getting a strange spectrum when trying to generate a single tone:
Settings: CGEN 200MHz.
DIQ1 BB interface sending single tone at full scale (12 bits)

TSG test:

CGEN set to 200MHz. Default TSG is TSPclk/8 (TSPclk = CGEN by default) so single tone should be at 200MHz/8 = 25MHz but in this case it is at 12.5MHz.
Output set to maximum gain.

  1. When sending a signal from FPGA:

  2. Modifying txpad gain to -30dB

Please advise,

Hello @Zack,
Sorry to bother you again, looking forward to your help in fixing this problem.

It looks like interpolation by 2 is engaged. In this case, as I wrote some time ago, tone frequency should be 200MHz/8/2 = 12.5MHz - this is what you correctly get.

It looks like you send the same sample to channel I as well as channel Q.

Hello @Zack,
For the spectrum, I am not sure why it would be an issue to send the same data on both I and Q.
I changed the data to I and Q = zeros and the spectrum is as follows:
I will work towards sending the correct Q, but did this to get a quick idea.
Does this look correct?

Hello @Zack,
Modified the design to produce both I and Q (sine and cosine) and getting the following output for a 6MHz tone.
Please advise.

Hi @EnthuMan,

It looks like you have timing issues at the interface. And I still think that you provide the same sample to both I and Q channels, while your wanted and image signals are the same. If sampling is OK, then you should get something similar as in your first picture in this thread.

Hello @Zack,
Please advise on how to fix it. Will checking it at digital loopback level help or is a it a problem between the read and write clocks of the TxFIFO?

Hello @Zack,
Is the read clock of the TxFIFO in digital loopback mode dependent on the interpolation setting?
Is the write clock of the RxFIFO dependent on the decimation setting int he digital loopback mode?
What would be very helpful also are all the settings needed for to properly configure digital loopback.
We are trying at our end but getting all kinds of data.



BB data loopback at LML port (assuming LML1 is BB2RF; LML2 is RF2BB. Assuming default values at startup):

  1. Set all the required TSP and LML registers as per your application;
  2. Set RX_MUX(0x002A[11:10]) = 01b;
  3. Set RXWRCLK_MUX(0x002A[1:0]) = 00b.