Single Tone Tx

System Development
1

Hello,
On our custom board we are trying to generate a single tone.
TxTSG with NCO output works fine.
The configuration is as follows:

  1. CGEN is set to 200MHz
  2. Interpolation ratio is set to 1
  3. FCLK1 is 200MHz and DIQ is at 400MSps
  4. 12bit LUT inside FPGA generates single tone at set frequency while sampling at 100MHz.
  5. I assume DAC sampling rate is independent of interpolation ratio and is decided by CGEN (in this case each channel of the DAC is sampling at 200MSps).
  6. SXT is configured to generate 2.25GHz
  7. Both I and Q are being fed the same single tone (not quadrature)

This is the output for 10MHz being generated

IMG_20190518_112941%20(Small)
IMG_20190518_112941%20(Small)640×480 52.2 KB

This is the output for 11.5MHz

IMG_20190518_140848%20(Small)
IMG_20190518_140848%20(Small)640×480 50.2 KB

An observation:

  1. Scaling my LUT output doesn’t change the output level at all.
    So bit shifting right by one bit should decrease the output by 6dB, but the output remains fixed.
    data_I <= LUT_I(11) & LUT_I(11) & LUT_I(11) & LUT_I(11) & LUT_I(11 downto 4);
    gives the same output as
    data_I <= LUT_I(11 downto 0);
    (the LUT is full scale).

  2. In fact for the 10MHz case feeding only the MSB also produced the same spectrum.
    i.e., data_I <= (others => LUT_I(11));

Thank you for looking into my issues,
Regards,

2

Hello @Zack,
Apologies, but I think this query could use your expertise.
Thanks,

3

Do you mean it is bypass or 2^1?

Frequency is too high, LMS7002M pins are not capable to operate at this frequency. You should not go higher than 120MHz.

Digital interface frequency, interpolation ratio and DAC frequency are dependent on each other and must be configured properly. For instance:

  1. CGEN frequency is 200MHz;
  2. CGEN is configured to provide 50MHz to TxTSP;
  3. Interpolation is set to 2^1;
  4. 2x2 MIMO configuration,
  5. According to these constraints, frequencies must be as follows:
    FCLK = 50MHz;
    TxTSP frequency is 50MHz (comming from CGEN);
    Signal sampling rate at LML interface is 25MHz per one MIMO channel;
    Signal sampling rate at DAC is 50MHz (because of interpolation by 2).
4

Hello @Zack,
Now we do not get any output from the IC. Is it possible that the wideband spectrum (in the previous post) could have damaged the IC?
We are able to program the IC and see the current changing when something is changed but there is no output.

5

Hello @Zack,
We “lowered” the noise floor and found the LO and the single tone there. Thank you with your approach we were able to make some progress.
The settings now are:

  1. CGEN set to 50MHz
  2. TxTSP clk is 50MHz
  3. Interpolation set to 2^1
  4. 2x2 MIMO configuration
  5. FCLK = 50MHz
  6. FPGA is sending data at 25MHz per MIMO channel
  7. DAC is sampling at 50MSps.
  8. Single tone of 10MHz.

The spectrum is as follows:

IMG_20190521_191108%20(Small)
IMG_20190521_191108%20(Small)640×480 50 KB

May I ask if you suggest why is there a tone at 5MHz? This happens as we the tone frequency is changed.

Point 2: It seems that the IC is damaged. Could excess power in the wideband spectrum have damaged the front end?

6

Hi @EnthuMan,

LMS7002M can withstand +10dBm (CW) power at the input.
What RF output do you use?

7

Hello @Zack,
I am referring to the Tx output from the LMS. The powers have suddenly dropped (please see the image in the previous post). The output signal which was around -20dBm earlier is now at -80dBm.
Regards,

8

Then I am not sure what do you mean by:

9

@Zack, the noisy spectrum (almost 200MHz wide) in a previous post in this topic.

10

You definitely can not damage LMS7 chip by sending some data.

11

Then what could the reason be? This device was working just fine (to whatever extent we were able to make it work) and now all of sudden the output levels have dropped. (both the channels).
Is there anything we can do to check?