Maximizing single channel RX bandwidth

Projects LimeSDR
1

Hello!

Lately I’ve been primarily using LimeSDR USB for single channel RX only. I’ve read in this post by @Zack that the bandwidth bottleneck of the device is the FPGA-FX3 bus. I was wondering if it was theoretically possible to achieve higher RF bandwidth by truncating samples to 8bits in the FPGA. For example to 120MHz. Can you please advise if this is feasible? Thanks.

2

Hi @OrsonMaxwell,

Let us calculate:

  1. 1x RX, 8 bit per sample: this setup will generate 240 MB/s data stream. No problem for Limesdr USB but it will require custom FPGA gateware.
  2. 1x RX, 12 bit per sample: this setup will generate 360 MB/s data stream. Even this shouldn’t be a problem for LimeSDR USB when using 12 bit compressed data stream. No need to modify FPGA gateware in this case.

Hope this helps.

3

Hello! Thanks for your quick response! Item 2 is interesting - do I need anything special in order to set the ADC to 120MSPS?

P.S. I do have very adequate cooling in case this can prove important in higher clock rates.

4

Ok a quick try with SoapySDR API gets me to 68MHz max then I start getting warning from the LMS driver like

[WARNING] SetPllFrequency: error configuring phase
[ERROR] LML TX phase search FAIL

Which makes me think that I’m doing something wrong with the TX channel. Currenly I’m doing absolutely nothing with it - I’m configuring RX only.