LimeSDR-PCIe max RX bandwidth

I’m currently attempting to evaluate if the LimeSDR-PCIe board is suitable for my needs. In previous topics on the forum I’m able to see that the board is bandwidth limited to ~200MB/s RX because of the Xillybus cores(in 2016 - with upgrades expected). When I look at the github gateware, I can see quite a bit of commits since 2016 - including DMA optimizations for PCIe transfers.

My question is - what is the highest number of 12-bit samples that can be transfered from FPGA->HOST, assuming minimal TX communication? Has the situation been improved from the ~200MB/s(~50MSPS uncompressed) in 2016?

The maximum data throughput that I am able to get with LimeSDR-PCIe is ~360-370MB/s in each direction.

Very interesting - thank you for your feedback.

Are the 360-370MB/s RX only, or RX/TX simultaneously?

360MB/s is much better for my application than 200MB/s - but I’d love to be able to recieve just above 400MB/s

~370 MB/s is for Rx/Tx simultaneously, but if I recall correctly 400MB/s per direction is the limit of Xillybus core, so you won’t be able to go above 400 MB/s. I have just tried Rx only in LimeSuiteGUI and the maximum that I am able to get is ~395 MB/s.