LimeSDR PCIe is 4x Gen1 per Cyclone IV GX FPGA transceiver limit.
On top of that, the Xillybus IP imposes a 400 MB/s upper limit which makes LimeSDR PCIe and USB GW identical in terms of bandwidth.
LimeSDR PCIe is 4x Gen1 per Cyclone IV GX FPGA transceiver limit.
On top of that, the Xillybus IP imposes a 400 MB/s upper limit which makes LimeSDR PCIe and USB GW identical in terms of bandwidth.