I’ve learned that there is an open source PCIe IP called RIFFA 2.2
Is there a plan to upgrade the LimeSDR PCIe with a FPGA which has a Gen2 transceiver (Cyclone IV GX is Gen1)? Maybe for the next Lime Transceiver generation?
And maybe the LimeSDR PCIe board can have a reduced price if the Xillybus license fee is removed and instead the RIFFA 2.2 PCIe IP is used?
- Xillybus has an upper limit of 400 MB/s in PCIe x4.
- RIFFA 2.2 claims a much higher limit due to the novel architecture
- In Cyclone V, I got these numbers from someone who is experimenting with this IP:
“I was seeing 209Mb/s for gen1_x1 and 411Mb/s for gen2_x1 settings.” - If this is reproducible in Cyclone IV, we would get 800Mbps (6.4Gbps), it is double the performance of Xillybus.
- In Cyclone V, I got these numbers from someone who is experimenting with this IP:
If LimeSDR PCIe is scheduled for an upgrade in the future, then a small Cyclone V GT with 5.0Gbps transceivers would give 18Gbps in Gen2 4x with Open Source RIFFA PCIe IP!!
References:
RIFFA 2.2
Cyclone IV Gen1 limit:
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-iv/cyiv-52001.pdf
Xillybus 400 MB/s upper limit:
http://xillybus.com/doc/xillybus-bandwidth
Reference discussion from @Zack