Has anyone tested LimeSDR PCIe in 4x Gen2 speed (18Gb/s)?
I would like to check if there is any tweak needed in the Xillybus IP to achieve Gen2 speeds.
LimeSDR PCIe is 4x Gen1 per Cyclone IV GX FPGA transceiver limit.
On top of that, the Xillybus IP imposes a 400 MB/s upper limit which makes LimeSDR PCIe and USB GW identical in terms of bandwidth.