LimeQuickTest failure: Signal loss on loopback test

f0nd004u · 13 July 2018 21:09

I bought the LimeSDR a while ago and it has been sitting in my projects backlog until this week. I bought the QRP enclosure and I am following their directions:

http://shop.qrp-labs.com/limesdr

I populated the 2-pin fan header and the LED headers. The LEDs and the fan work fine; I’ve got TX and RX lights and the FPGA1 light on.

I ran self test last week and it came back all good, but after doing this work I ran it again and CH0 is experiencing serious signal loss on LNA-H when looping back from TX2 at 2500MHz. I have pasted my test results below.

It kinda seems clear that I have done this damage considering the chain of events. My board is still usable via the other antenna inputs but this is a huge bummer. Is there any way for me to fix this? Any ideas about what component I fried?

I’d like to spare the internet pictures of my terrible soldering; it looks like I may have toasted the corner of IC1-7 a little bit but I definitely didn’t short anything.

Thanks for the help!

radiodev@cd6dee7a0082:~$ LimeQuickTest
[ TESTING STARTED ]
->Start time: Fri Jul 13 20:52:17 2018

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009070602442B3B
Serial Number: 0009070602442B3B

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 32024; 35780; 39536 - PASSED
->Si5351C test
CLK0: 17553 / 17554 - PASSED
CLK1: 17553 / 17554 - PASSED
CLK2: 17553 / 17554 - PASSED
CLK3: 17553 / 17554 - PASSED
CLK4: 17553 / 17554 - PASSED
CLK5: 17553 / 17554 - PASSED
CLK6: 17553 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112895 (min); 5113029 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 09 04 11 09 04 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.7 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-17.6 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-17.3 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-20.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-42.1 dBFS, 5.00 MHz) - FAILED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-14.7 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 1.53 seconds

f0nd004u · 13 July 2018 22:20

Now LNA_H tests are failing on both CH0 and CH1

radiodev@cd6dee7a0082:~$ LimeQuickTest
[ TESTING STARTED ]
->Start time: Fri Jul 13 22:19:44 2018

->Device: LimeSDR-USB, media=USB 2.0, module=FX3, addr=1d50:6108, serial=0009070602442B3B
Warning: USB3 not available
Serial Number: 0009070602442B3B

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 23709; 27465; 31221 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112907 (min); 5113042 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 09 04 11 09 04 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-14.0 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-16.7 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-18.8 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-43.0 dBFS, 5.00 MHz) - FAILED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-36.8 dBFS, 5.00 MHz) - FAILED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 2.17 seconds

f0nd004u · 13 July 2018 22:30

I think I figured it out… in my manhandling the board I broke one side of the connections to the transformers at T4 and T7. From looking in the forums, other people have done this as well.

The transformers themselves look ok, I just broke the connections, I’m going to attempt a repair.

f0nd004u · 14 July 2018 00:44

For reference. This is why I can’t have nice things.

andrewback · 24 July 2018 12:37

Sorry to hear this

Good luck with the fix, but I have a feeling you may end up needing to replace the transformers.

DUO · 9 November 2018 16:56

I got mine failed too on LNAH :

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-14.3 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-16.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-18.4 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-20.0 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-66.1 dBFS, 5.00 MHz) - FAILED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-15.0 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

=> Board tests FAILED <=

but it works fine below 2400mhz.

what should I do?

best,
DUO

IgnasJ · 9 November 2018 18:43

It looks like something on TX1_2 or RX1_H port is damaged. Check if you can see any visible damage to the components (e.g. broken coil) on these ports.

pe2ben · 13 January 2019 23:25

Hello @IgnasJ,

is my board also defective or is it acceptable?

Regards Ben

LimeQuickTest
[ TESTING STARTED ]
->Start time: Mon Jan 14 00:20:41 2019

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009062000C41038
Serial Number: 0009062000C41038

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 21434; 25190; 28946 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112948 (min); 5113072 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 05 0F 11 05 0F 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.5 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-17.6 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-19.8 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-22.7 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-18.3 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-15.9 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 1.48 seconds