One of my boards, that I’ve been using for years, seems to have a problem. I already tried reflashing it (FW+GW through LimeSuite GUI) but it doesn’t fix the issue. When connecting to it through Soapy on Win10 and Ubuntu 20.04 or 22.04, I get errors at once:
[INFO] Make connection: 'LimeSDR-USB [USB 3.0] 9070602463416'
[INFO] Reference clock 30.72 MHz
[INFO] Device name: LimeSDR-USB
[INFO] Reference: 30.72 MHz
[ERROR] SetFrequencySXT(1250 MHz) - cannot deliver frequency
[INFO] LMS7002M calibration values caching Disable
[ERROR] TuneVCO(CGEN) - failed to lock (cmphl!=0)
[ERROR] SetFrequencyCGEN(80 MHz) failed
[ERROR] TuneVCO(CGEN) - failed to lock (cmphl!=0)
[ERROR] SetFrequencyCGEN(440 MHz) failed
I ran LimeQuickTest on Win10 and got the following.
[ TESTING STARTED ]
->Start time: Wed May 18 11:07:40 2022
->LimeSuite version: 20.10.0-PothosSDR-2021.07.25-vc16-x64
->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009070602463416, index=0, HW=4, GW=2.23
Serial Number: 0009070602463416
Temperature internal ADC calibration failed
Chip temperature: 0 C
[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 19093; 22849; 26605 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112969 (min); 5113098 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 03 02 12 03 02 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTest() failed
->LMS7002M Test FAILED
[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(61.44 MHz) failed
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 1.42 seconds
@ricardas Any idea?