i get this error suddenly
“[12:54:02] INFO: Reference clock 30.72 MHz
[12:54:02] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.23 Ref Clk: 30.72 MHz
[12:54:51] ERROR: TuneVCO(CGEN) - failed to lock (cmphl!=0)
[12:54:51] ERROR: SetFrequencyCGEN(61.44 MHz) failed“
using LimeQuickTest i get
“[ TESTING STARTED ]
->Start time: Wed Nov 5 14:34:21 2025
->LimeSuite version: 20.10.0-g1480bfea
->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=000907060244272D, index=0, HW=4, GW=2.23
Serial Number: 000907060244272D
Chip temperature: 45 C
[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 34947; 38703; 42459 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112999 (min); 5113139 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 0C 06 12 0C 06 08
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(61.44 MHz) failed
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 1.47 seconds“
it was work before then i get this message