Lime SDR crashes when frequency change


#1

Hello,

I’m trying to work with LimeSDR USB with newest version of SDR-Radio and HDSDR software. In general, board is working OK when not changing RX frequency. When I want to change frequency, there is what happens very often:

20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### SetFrequencySXR(125.606 MHz) - cannot deliver frequency
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeSDR> Get RX channel 0 center frequency: -0.012kHz, -12.0
20:34:08.454: Radio LimeSDR> Error (Set:125605844.000000, get:-12.000000), retrying…
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed
20:34:08.454: Radio LimeAPI> ### API Dbg Lvl 1 ### Write(64 bytes) failed

I’m using Win10. Was trying direct USB3.0, USB3.0 via powered hub, direct USB2.0, with and without external power supply…

I would be very grateful for any help.

Best regards,
Tomek.


#2

This is LimeQuickTest result after crash in SDRConsole:

[ TESTING STARTED ]
->Start time: Sun Feb 10 08:39:44 2019

Gateware version mismatch!
Expected gateware version 2, revision 17
But found version 0, revision 0
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009062A00CE2B1A, index=0
Serial Number: 0009062A00CE2B1A

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 1; 0; 0 - PASSED
->Si5351C test
CLK0: 2 / 17554 - FAILED
CLK1: 2 / 17554 - FAILED
CLK2: 2 / 17554 - FAILED
CLK3: 2 / 17554 - FAILED
CLK4: 2 / 17554 - FAILED
CLK5: 2 / 17554 - FAILED
CLK6: 2 / 17554 - FAILED
FAILED
->ADF4002 Test
Result: 0 - FAILED
FAILED
->VCTCXO test
Results : 4 (min); 4 (max) - FAILED
FAILED
->Clock Network Test FAILED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 05 11 11 05 11 03
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTest() failed
->LMS7002M Test FAILED

[ RF Loopback Test ]
->Configure LMS
SetFrequencySXT(1250 MHz) - cannot deliver frequency
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 2.06 seconds

After restarting LimeSDR everything is OK:

[ TESTING STARTED ]
->Start time: Sun Feb 10 08:42:35 2019

Gateware version mismatch!
Expected gateware version 2, revision 17
But found version 2, revision 18
Follow the FW and FPGA upgrade instructions:
http://wiki.myriadrf.org/Lime_Suite#Flashing_images
Or run update on the command line: LimeUtil --update

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009062A00CE2B1A, index=0
Serial Number: 0009062A00CE2B1A

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 27410; 31166; 34922 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112933 (min); 5113066 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 11 05 11 11 05 11 03
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-13.6 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.9 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-13.1 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-19.2 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-14.9 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-13.4 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests PASSED <=

Elapsed time: 5.74 seconds