My setup is as picturesd below - i’m synchronizing two xtrx’s for 4 channel phase coherent receive. I split a CW tone close to my LO frequency and feed it into all 4 channels across 2 xtrx’s
Does anyone know the expected phase error across boards? I’d expect it to be, maybe, at worst case, close to 2x the integrated phase noise at the LO i’m operating at, but this is only about 0.6 degrees and i’m experience about 10-15 degrees
i’m getting about 0.20-0.3 radians which is quite substantial and i imagine thats from the fractional-N PLLs in each lms7002 which would be non-deterministic across boards. Is it advised to use non-fractional modes for better coherence?
it also seem that there is no deterministic phase coherence from start up to start up or LO change. That is the lms7002 is capable of phase lock (to some degree of error inter-chip), but if you wanted phase coherence (deterministic phase lock every startup/between LO changes) that is simply not possible as the PLL randomly relocks its fractional-N pll between chips thus making phase difference between channels across chips random and requiring a recalibration step after every LO change?
heres some actual data if it helps. i have also confirmed an LO tuning means non-deterministic phase difference between all channels, i suspect there is no way to remedy this and any LO change would need a calibration step.Theres also a lot of phase drift between two chips after calibration (see gif below).
I’ve also found that interchip phase noise increases as sample rate increases, but i haven’t pinpointed why
Anyone from Lime have any recommendations on this issue? i can reproduce this over multiple custom boards and with multiple XTRXs @andrewback@VytautasB@Zack
Thanks @VytautasB. Yes definitely more of a a RF systems question, but specifically wondering if theres anyway to get determinism out of the PLLs across chips, and if this temperature behavior is expected it suggests the LO is moving a ton with very little temperature change.
XTRX is GW 3.5 (litex version), second xtrx register 0018 has been configured to 0004 iusing limeSPI.
clock network is similar on custom boards.
has anyone at lime looked into phase lock between multiple chips?
thanks, understood. can any engineers from lime focused on the rf side + the lo/pll comment on multi-chip synchronization, phase error, and phase drift of the LO / PLLs with temperature.
